2019-05-14 17:37:11 +07:00
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m0plus \
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-nostdlib \
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-DCORE_M0PLUS \
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-D__VTOR_PRESENT=0 \
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-D__USE_LPCOPEN \
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2019-09-03 13:25:36 +07:00
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-DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
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2019-05-14 17:51:05 +07:00
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
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-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
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2019-05-14 17:37:11 +07:00
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2019-09-09 12:23:03 +07:00
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MCU_DIR = hw/mcu/nxp/lpc_driver/lpc11u6x/lpc_chip_11u6x
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2019-09-06 12:07:48 +07:00
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2019-05-14 17:37:11 +07:00
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/lpcxpresso11u68/lpc11u68.ld
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SRC_C += \
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2019-09-09 12:39:58 +07:00
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$(MCU_DIR)/../gcc/cr_startup_lpc11u6x.c \
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2019-09-09 12:23:03 +07:00
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$(MCU_DIR)/src/chip_11u6x.c \
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$(MCU_DIR)/src/clock_11u6x.c \
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$(MCU_DIR)/src/gpio_11u6x.c \
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$(MCU_DIR)/src/iocon_11u6x.c \
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|
$(MCU_DIR)/src/syscon_11u6x.c \
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|
$(MCU_DIR)/src/sysinit_11u6x.c
|
2019-05-14 17:37:11 +07:00
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|
|
INC += \
|
2019-09-09 12:23:03 +07:00
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|
$(TOP)/$(MCU_DIR)/inc
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2019-05-14 17:37:11 +07:00
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# For TinyUSB port source
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VENDOR = nxp
|
2019-09-01 16:44:40 +07:00
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|
CHIP_FAMILY = lpc_ip3511
|
2019-05-14 17:37:11 +07:00
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|
# For freeRTOS port source
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|
|
FREERTOS_PORT = ARM_CM0
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|
# For flash-jlink target
|
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|
|
JLINK_DEVICE = LPC11U68
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|
|
JLINK_IF = swd
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|
2019-09-01 21:04:43 +07:00
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|
|
# flash using pyocd
|
|
|
|
|
flash: $(BUILD)/$(BOARD)-firmware.hex
|
|
|
|
|
pyocd flash -t lpc11u68 $<
|
