712 lines
40 KiB
C
712 lines
40 KiB
C
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/**********************************************************************
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* $Id$ lpc17xx_emac.h 2010-05-21
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*//**
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* @file lpc17xx_emac.h
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* @brief Contains all macro definitions and function prototypes
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* support for Ethernet MAC firmware library on LPC17xx
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* @version 2.0
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* @date 21. May. 2010
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2010, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup EMAC EMAC (Ethernet Media Access Controller)
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_EMAC_H_
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#define LPC17XX_EMAC_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define MCB_LPC_1768
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//#define IAR_LPC_1768
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup EMAC_Public_Macros EMAC Public Macros
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* @{
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*/
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/* EMAC PHY status type definitions */
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#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
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#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
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#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
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/* EMAC PHY device Speed definitions */
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#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
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#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
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#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
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#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
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#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
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/**
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* @}
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*/
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup EMAC_Private_Macros EMAC Private Macros
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* @{
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*/
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/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
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#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
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#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
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#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
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#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
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/* --------------------- BIT DEFINITIONS -------------------------------------- */
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/*********************************************************************//**
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* Macro defines for MAC Configuration Register 1
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**********************************************************************/
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#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
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#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
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#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
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#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
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#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
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#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
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#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
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#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
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#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
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#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
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#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
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/*********************************************************************//**
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* Macro defines for MAC Configuration Register 2
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**********************************************************************/
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#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
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#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
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#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
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#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
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#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
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#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
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#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
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#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
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#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
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#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
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#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
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#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
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#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
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/*********************************************************************//**
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* Macro defines for Back-to-Back Inter-Packet-Gap Register
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**********************************************************************/
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/** Programmable field representing the nibble time offset of the minimum possible period
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* between the end of any transmitted packet to the beginning of the next */
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#define EMAC_IPGT_BBIPG(n) (n&0x7F)
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/** Recommended value for Full Duplex of Programmable field representing the nibble time
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* offset of the minimum possible period between the end of any transmitted packet to the
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* beginning of the next */
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#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
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/** Recommended value for Half Duplex of Programmable field representing the nibble time
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* offset of the minimum possible period between the end of any transmitted packet to the
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* beginning of the next */
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#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
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/*********************************************************************//**
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* Macro defines for Non Back-to-Back Inter-Packet-Gap Register
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**********************************************************************/
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/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
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#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
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/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
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#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
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/** Programmable field representing the optional carrierSense window referenced in
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* IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
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#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
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/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
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#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
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/*********************************************************************//**
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* Macro defines for Collision Window/Retry Register
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**********************************************************************/
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/** Programmable field specifying the number of retransmission attempts following a collision before
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* aborting the packet due to excessive collisions */
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#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
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/** Programmable field representing the slot time or collision window during which collisions occur
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* in properly configured networks */
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#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
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/** Default value for Collision Window / Retry register */
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#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
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/*********************************************************************//**
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* Macro defines for Maximum Frame Register
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**********************************************************************/
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/** Represents a maximum receive frame of 1536 octets */
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#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
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/*********************************************************************//**
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* Macro defines for PHY Support Register
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**********************************************************************/
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#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
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//#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
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/*********************************************************************//**
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* Macro defines for Test Register
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**********************************************************************/
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#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
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#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
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#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
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/*********************************************************************//**
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* Macro defines for MII Management Configuration Register
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**********************************************************************/
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#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
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#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
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#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
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#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
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#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
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/*********************************************************************//**
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* Macro defines for MII Management Command Register
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**********************************************************************/
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#define EMAC_MCMD_READ 0x00000001 /**< MII Read */
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#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
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#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
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#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
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/*********************************************************************//**
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* Macro defines for MII Management Address Register
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**********************************************************************/
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#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
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#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
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/*********************************************************************//**
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* Macro defines for MII Management Write Data Register
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**********************************************************************/
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#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
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/*********************************************************************//**
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* Macro defines for MII Management Read Data Register
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**********************************************************************/
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#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
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/*********************************************************************//**
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* Macro defines for MII Management Indicators Register
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**********************************************************************/
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#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
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#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
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#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
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#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
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/* Station Address 0 Register */
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/* Station Address 1 Register */
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/* Station Address 2 Register */
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/* Control register definitions --------------------------------------------------------------------------- */
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/*********************************************************************//**
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* Macro defines for Command Register
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**********************************************************************/
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#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
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#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
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#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
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#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
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#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
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#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
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#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
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#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
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#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
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#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
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/*********************************************************************//**
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* Macro defines for Status Register
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**********************************************************************/
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#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
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#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
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/*********************************************************************//**
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* Macro defines for Transmit Status Vector 0 Register
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**********************************************************************/
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#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
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#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
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#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
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#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
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#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
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#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
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#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
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#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
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#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
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#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
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#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
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#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
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#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
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#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
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#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
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#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
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#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
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/*********************************************************************//**
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* Macro defines for Transmit Status Vector 1 Register
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**********************************************************************/
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#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
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#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
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/*********************************************************************//**
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* Macro defines for Receive Status Vector Register
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**********************************************************************/
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#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
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#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
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#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
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#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
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#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
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#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
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#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
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#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
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#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
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#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
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#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
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#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
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#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
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#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
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#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
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#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
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/*********************************************************************//**
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* Macro defines for Flow Control Counter Register
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**********************************************************************/
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#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
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#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
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/*********************************************************************//**
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* Macro defines for Flow Control Status Register
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**********************************************************************/
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#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
|
||
|
|
|
||
|
|
|
||
|
|
/* Receive filter register definitions -------------------------------------------------------- */
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for Receive Filter Control Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
|
||
|
|
#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
|
||
|
|
#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
|
||
|
|
#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
|
||
|
|
#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
|
||
|
|
#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
|
||
|
|
#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
|
||
|
|
#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for Receive Filter WoL Status/Clear Registers
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
|
||
|
|
#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
|
||
|
|
#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
|
||
|
|
#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
|
||
|
|
#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
|
||
|
|
#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
|
||
|
|
#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
|
||
|
|
#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
|
||
|
|
#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
|
||
|
|
|
||
|
|
|
||
|
|
/* Module control register definitions ---------------------------------------------------- */
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for Interrupt Status/Enable/Clear/Set Registers
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
|
||
|
|
#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
|
||
|
|
#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
|
||
|
|
#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
|
||
|
|
#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
|
||
|
|
#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
|
||
|
|
#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
|
||
|
|
#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
|
||
|
|
#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
|
||
|
|
#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for Power Down Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
|
||
|
|
|
||
|
|
/* Descriptor and status formats ---------------------------------------------------- */
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for RX Descriptor Control Word
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
|
||
|
|
#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for RX Status Hash CRC Word
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
|
||
|
|
#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for RX Status Information Word
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
|
||
|
|
#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
|
||
|
|
#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
|
||
|
|
#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
|
||
|
|
#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
|
||
|
|
#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
|
||
|
|
#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
|
||
|
|
#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
|
||
|
|
#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
|
||
|
|
#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
|
||
|
|
#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
|
||
|
|
#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
|
||
|
|
#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
|
||
|
|
#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
|
||
|
|
#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
|
||
|
|
#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
|
||
|
|
EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for TX Descriptor Control Word
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
|
||
|
|
#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
|
||
|
|
#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
|
||
|
|
#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
|
||
|
|
#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
|
||
|
|
#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
|
||
|
|
#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for TX Status Information Word
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
|
||
|
|
#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
|
||
|
|
#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
|
||
|
|
#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
|
||
|
|
#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
|
||
|
|
#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
|
||
|
|
#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
|
||
|
|
#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
|
||
|
|
|
||
|
|
#ifdef MCB_LPC_1768
|
||
|
|
/* DP83848C PHY definition ------------------------------------------------------------ */
|
||
|
|
|
||
|
|
/** PHY device reset time out definition */
|
||
|
|
#define EMAC_PHY_RESP_TOUT 0x100000UL
|
||
|
|
|
||
|
|
/* ENET Device Revision ID */
|
||
|
|
#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for DP83848C PHY Registers
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
|
||
|
|
#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
|
||
|
|
#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
|
||
|
|
#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
|
||
|
|
#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
|
||
|
|
#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
|
||
|
|
#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
|
||
|
|
#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
|
||
|
|
#define EMAC_PHY_REG_LPNPA 0x08
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Extended Registers
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_REG_STS 0x10 /**< Status Register */
|
||
|
|
#define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
|
||
|
|
#define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
|
||
|
|
#define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
|
||
|
|
#define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
|
||
|
|
#define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
|
||
|
|
#define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
|
||
|
|
#define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
|
||
|
|
#define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
|
||
|
|
#define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
|
||
|
|
#define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
|
||
|
|
#define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Basic Mode Control Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
|
||
|
|
#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
|
||
|
|
#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
|
||
|
|
#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
|
||
|
|
#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
|
||
|
|
#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
|
||
|
|
#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
|
||
|
|
#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Basic Mode Status Status Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
|
||
|
|
#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
|
||
|
|
#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
|
||
|
|
#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
|
||
|
|
#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
|
||
|
|
#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
|
||
|
|
#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
|
||
|
|
#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
|
||
|
|
#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
|
||
|
|
#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Status Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
|
||
|
|
#define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
|
||
|
|
#define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
|
||
|
|
#define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
|
||
|
|
#define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
|
||
|
|
#define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
|
||
|
|
#define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
|
||
|
|
|
||
|
|
#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
|
||
|
|
#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
|
||
|
|
#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
|
||
|
|
#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
|
||
|
|
#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
|
||
|
|
|
||
|
|
#define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
|
||
|
|
#define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
|
||
|
|
|
||
|
|
#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
|
||
|
|
#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
|
||
|
|
#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
|
||
|
|
|
||
|
|
#elif defined(IAR_LPC_1768)
|
||
|
|
/* KSZ8721BL PHY definition ------------------------------------------------------------ */
|
||
|
|
/** PHY device reset time out definition */
|
||
|
|
#define EMAC_PHY_RESP_TOUT 0x100000UL
|
||
|
|
|
||
|
|
/* ENET Device Revision ID */
|
||
|
|
#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for KSZ8721BL PHY Registers
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
|
||
|
|
#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
|
||
|
|
#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
|
||
|
|
#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
|
||
|
|
#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
|
||
|
|
#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
|
||
|
|
#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
|
||
|
|
#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
|
||
|
|
#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
|
||
|
|
#define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
|
||
|
|
#define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
|
||
|
|
#define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Basic Mode Control Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
|
||
|
|
#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
|
||
|
|
#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
|
||
|
|
#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
|
||
|
|
#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
|
||
|
|
#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
|
||
|
|
#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
|
||
|
|
#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
|
||
|
|
#define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
|
||
|
|
#define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Basic Mode Status Register
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
|
||
|
|
#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
|
||
|
|
#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
|
||
|
|
#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
|
||
|
|
#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
|
||
|
|
#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
|
||
|
|
#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
|
||
|
|
#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
|
||
|
|
#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
|
||
|
|
#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
|
||
|
|
#define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
|
||
|
|
#define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for PHY Identifier
|
||
|
|
**********************************************************************/
|
||
|
|
/* PHY Identifier 1 bitmap definitions */
|
||
|
|
#define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
|
||
|
|
|
||
|
|
/* PHY Identifier 2 bitmap definitions */
|
||
|
|
#define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
|
||
|
|
|
||
|
|
/*********************************************************************//**
|
||
|
|
* Macro defines for Auto-Negotiation Advertisement
|
||
|
|
**********************************************************************/
|
||
|
|
#define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
|
||
|
|
#define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
|
||
|
|
#define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
|
||
|
|
#define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
|
||
|
|
#define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
|
||
|
|
#define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
|
||
|
|
#define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
|
||
|
|
#define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
|
||
|
|
#define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
|
||
|
|
|
||
|
|
#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
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#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
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#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
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#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
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#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
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||
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#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
|
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#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
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#define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
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#define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
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#endif
|
||
|
|
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||
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/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
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|
|
||
|
|
/* Public Types --------------------------------------------------------------- */
|
||
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/** @defgroup EMAC_Public_Types EMAC Public Types
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Descriptor and status formats ---------------------------------------------- */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief RX Descriptor structure type definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
uint32_t Packet; /**< Receive Packet Descriptor */
|
||
|
|
uint32_t Ctrl; /**< Receive Control Descriptor */
|
||
|
|
} RX_Desc;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief RX Status structure type definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
uint32_t Info; /**< Receive Information Status */
|
||
|
|
uint32_t HashCRC; /**< Receive Hash CRC Status */
|
||
|
|
} RX_Stat;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief TX Descriptor structure type definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
uint32_t Packet; /**< Transmit Packet Descriptor */
|
||
|
|
uint32_t Ctrl; /**< Transmit Control Descriptor */
|
||
|
|
} TX_Desc;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief TX Status structure type definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
uint32_t Info; /**< Transmit Information Status */
|
||
|
|
} TX_Stat;
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief TX Data Buffer structure definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
uint32_t ulDataLen; /**< Data length */
|
||
|
|
uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
|
||
|
|
} EMAC_PACKETBUF_Type;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief EMAC configuration structure definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
|
||
|
|
- EMAC_MODE_AUTO
|
||
|
|
- EMAC_MODE_10M_FULL
|
||
|
|
- EMAC_MODE_10M_HALF
|
||
|
|
- EMAC_MODE_100M_FULL
|
||
|
|
- EMAC_MODE_100M_HALF
|
||
|
|
*/
|
||
|
|
uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
|
||
|
|
of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
|
||
|
|
*/
|
||
|
|
} EMAC_CFG_Type;
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* Public Functions ----------------------------------------------------------- */
|
||
|
|
/** @defgroup EMAC_Public_Functions EMAC Public Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Init/DeInit EMAC peripheral */
|
||
|
|
Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
|
||
|
|
void EMAC_DeInit(void);
|
||
|
|
|
||
|
|
/* PHY functions --------------*/
|
||
|
|
int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
|
||
|
|
int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
|
||
|
|
int32_t EMAC_UpdatePHYStatus(void);
|
||
|
|
|
||
|
|
/* Filter functions ----------*/
|
||
|
|
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
|
||
|
|
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
|
||
|
|
|
||
|
|
/* EMAC Packet Buffer functions */
|
||
|
|
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
|
||
|
|
void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
|
||
|
|
|
||
|
|
/* EMAC Interrupt functions -------*/
|
||
|
|
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
|
||
|
|
IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
|
||
|
|
|
||
|
|
/* EMAC Index functions -----------*/
|
||
|
|
Bool EMAC_CheckReceiveIndex(void);
|
||
|
|
Bool EMAC_CheckTransmitIndex(void);
|
||
|
|
void EMAC_UpdateRxConsumeIndex(void);
|
||
|
|
void EMAC_UpdateTxProduceIndex(void);
|
||
|
|
|
||
|
|
FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
|
||
|
|
uint32_t EMAC_GetReceiveDataSize(void);
|
||
|
|
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* LPC17XX_EMAC_H_ */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* --------------------------------- End Of File ------------------------------ */
|