tinyUSB/hw/bsp/stm32f411disco/board.mk

CFLAGS += \
  -flto \
  -mthumb \
  -mabi=aapcs \
  -mcpu=cortex-m4 \
  -mfloat-abi=hard \
  -mfpu=fpv4-sp-d16 \
  -nostdlib -nostartfiles \
  -DSTM32F411xE \
  -DCFG_TUSB_MCU=OPT_MCU_STM32F4

# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=cast-align

ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F4xx

# All source paths should be relative to the top level.
LD_FILE = hw/bsp/$(BOARD)/STM32F411VETx_FLASH.ld

SRC_C += \
	$(ST_CMSIS)/Source/Templates/system_stm32f4xx.c \
	$(ST_HAL_DRIVER)/Src/stm32f4xx_hal.c \
	$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_cortex.c \
	$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_rcc.c \
	$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_uart.c \
	$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_gpio.c

SRC_S += \
	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s

INC += \
	$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
	$(TOP)/$(ST_CMSIS)/Include \
	$(TOP)/$(ST_HAL_DRIVER)/Inc \
	$(TOP)/hw/bsp/$(BOARD)

# For TinyUSB port source
VENDOR = st
CHIP_FAMILY = synopsys

# For freeRTOS port source
FREERTOS_PORT = ARM_CM4F

# For flash-jlink target
JLINK_DEVICE = stm32f411ve

# flash target using on-board stlink
flash: flash-stlink
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00			`CFLAGS += \`
move -flto to board.mk current board that doesn work with flto is spresense and mimxrt10xx (due to xip image_vector_table is optimized out). 2019-11-20 16:06:40 +07:00			`-flto \`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00			`-mthumb \`
switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`-mabi=aapcs \`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00			`-mcpu=cortex-m4 \`
			`-mfloat-abi=hard \`
			`-mfpu=fpv4-sp-d16 \`
switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`-nostdlib -nostartfiles \`
move -flto to board.mk current board that doesn work with flto is spresense and mimxrt10xx (due to xip image_vector_table is optimized out). 2019-11-20 16:06:40 +07:00			`-DSTM32F411xE \`
switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`-DCFG_TUSB_MCU=OPT_MCU_STM32F4`

enable -Wcast-align suppress vendor sdk driver at board.mk 2020-05-17 14:24:15 +07:00			`# suppress warning caused by vendor mcu driver`
			`CFLAGS += -Wno-error=cast-align`

switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver`
			`ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F4xx`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`# All source paths should be relative to the top level.`
ported stm32f2, added board stm32f207zg nucleo close #127 2019-09-12 10:41:03 +07:00			`LD_FILE = hw/bsp/$(BOARD)/STM32F411VETx_FLASH.ld`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`SRC_C += \`
switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`$(ST_CMSIS)/Source/Templates/system_stm32f4xx.c \`
			`$(ST_HAL_DRIVER)/Src/stm32f4xx_hal.c \`
			`$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_cortex.c \`
			`$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_rcc.c \`
Update UARTs for stm32f4xx discovery boards. Other minor cleanups. 2020-03-28 11:19:50 -04:00			`$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_uart.c \`
stm32: Refactor so F4 and H7 use a single Synopsys IP source file. 2019-09-09 10:48:14 -04:00			`$(ST_HAL_DRIVER)/Src/stm32f4xx_hal_gpio.c`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`SRC_S += \`
switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`INC += \`
switch stm32f4 to use st_driver submodule 2019-09-05 22:12:43 +07:00			`$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \`
			`$(TOP)/$(ST_CMSIS)/Include \`
			`$(TOP)/$(ST_HAL_DRIVER)/Inc \`
			`$(TOP)/hw/bsp/$(BOARD)`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`# For TinyUSB port source`
			`VENDOR = st`
stm32: Refactor so F4 and H7 use a single Synopsys IP source file. 2019-09-09 10:48:14 -04:00			`CHIP_FAMILY = synopsys`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`# For freeRTOS port source`
			`FREERTOS_PORT = ARM_CM4F`

			`# For flash-jlink target`
added stm32f411 blackpill 2020-01-10 00:28:46 +07:00			`JLINK_DEVICE = stm32f411ve`
adding stm32f411 disco compile ok 2019-07-19 21:19:06 +07:00
			`# flash target using on-board stlink`
clean up flash-stlink 2020-01-10 15:09:59 +07:00			`flash: flash-stlink`