385 lines
16 KiB
C
385 lines
16 KiB
C
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/**********************************************************************
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* $Id$ lpc17xx_i2s.h 2011-06-06
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*//**
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* @file lpc17xx_i2s.h
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* @brief Contains all macro definitions and function prototypes
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* support for I2S firmware library on LPC17xx
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* @version 3.1
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* @date 06. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup I2S I2S (Inter-IC Sound bus)
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_I2S_H_
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#define LPC17XX_I2S_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup I2S_Public_Macros I2S Public Macros
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* @{
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*/
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/*********************************************************************//**
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* I2S configuration parameter defines
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**********************************************************************/
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/** I2S Wordwidth bit */
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#define I2S_WORDWIDTH_8 ((uint32_t)(0))
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#define I2S_WORDWIDTH_16 ((uint32_t)(1))
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#define I2S_WORDWIDTH_32 ((uint32_t)(3))
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/** I2S Channel bit */
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#define I2S_STEREO ((uint32_t)(0))
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#define I2S_MONO ((uint32_t)(1))
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/** I2S Master/Slave mode bit */
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#define I2S_MASTER_MODE ((uint8_t)(0))
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#define I2S_SLAVE_MODE ((uint8_t)(1))
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/** I2S Stop bit */
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#define I2S_STOP_ENABLE ((uint8_t)(1))
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#define I2S_STOP_DISABLE ((uint8_t)(0))
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/** I2S Reset bit */
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#define I2S_RESET_ENABLE ((uint8_t)(1))
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#define I2S_RESET_DISABLE ((uint8_t)(0))
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/** I2S Mute bit */
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#define I2S_MUTE_ENABLE ((uint8_t)(1))
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#define I2S_MUTE_DISABLE ((uint8_t)(0))
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/** I2S Transmit/Receive bit */
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#define I2S_TX_MODE ((uint8_t)(0))
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#define I2S_RX_MODE ((uint8_t)(1))
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/** I2S Clock Select bit */
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#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
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#define I2S_CLKSEL_MCLK ((uint8_t)(2))
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/** I2S 4-pin Mode bit */
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#define I2S_4PIN_ENABLE ((uint8_t)(1))
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#define I2S_4PIN_DISABLE ((uint8_t)(0))
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/** I2S MCLK Enable bit */
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#define I2S_MCLK_ENABLE ((uint8_t)(1))
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#define I2S_MCLK_DISABLE ((uint8_t)(0))
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/** I2S select DMA bit */
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#define I2S_DMA_1 ((uint8_t)(0))
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#define I2S_DMA_2 ((uint8_t)(1))
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/**
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* @}
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*/
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup I2S_Private_Macros I2S Private Macros
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* @{
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*/
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/*********************************************************************//**
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* Macro defines for DAO-Digital Audio Output register
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**********************************************************************/
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/** I2S wordwide - the number of bytes in data*/
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#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
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#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
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#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
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/** I2S control mono or stereo format */
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#define I2S_DAO_MONO ((uint32_t)(1<<2))
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/** I2S control stop mode */
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#define I2S_DAO_STOP ((uint32_t)(1<<3))
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/** I2S control reset mode */
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#define I2S_DAO_RESET ((uint32_t)(1<<4))
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/** I2S control master/slave mode */
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#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
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/** I2S word select half period minus one */
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#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
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/** I2S control mute mode */
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#define I2S_DAO_MUTE ((uint32_t)(1<<15))
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/*********************************************************************//**
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* Macro defines for DAI-Digital Audio Input register
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**********************************************************************/
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/** I2S wordwide - the number of bytes in data*/
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#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
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#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
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#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
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/** I2S control mono or stereo format */
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#define I2S_DAI_MONO ((uint32_t)(1<<2))
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/** I2S control stop mode */
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#define I2S_DAI_STOP ((uint32_t)(1<<3))
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/** I2S control reset mode */
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#define I2S_DAI_RESET ((uint32_t)(1<<4))
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/** I2S control master/slave mode */
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#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
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/** I2S word select half period minus one (9 bits)*/
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#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
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/** I2S control mute mode */
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#define I2S_DAI_MUTE ((uint32_t)(1<<15))
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/*********************************************************************//**
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* Macro defines for STAT register (Status Feedback register)
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**********************************************************************/
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/** I2S Status Receive or Transmit Interrupt */
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#define I2S_STATE_IRQ ((uint32_t)(1))
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/** I2S Status Receive or Transmit DMA1 */
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#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
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/** I2S Status Receive or Transmit DMA2 */
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#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
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/** I2S Status Current level of the Receive FIFO (5 bits)*/
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#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
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/** I2S Status Current level of the Transmit FIFO (5 bits)*/
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#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
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/*********************************************************************//**
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* Macro defines for DMA1 register (DMA1 Configuration register)
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**********************************************************************/
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/** I2S control DMA1 for I2S receive */
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#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
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/** I2S control DMA1 for I2S transmit */
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#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
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/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
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#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
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/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
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#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
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/*********************************************************************//**
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* Macro defines for DMA2 register (DMA2 Configuration register)
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**********************************************************************/
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/** I2S control DMA2 for I2S receive */
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#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
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/** I2S control DMA1 for I2S transmit */
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#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
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/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
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#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
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/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
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#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
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/*********************************************************************//**
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* Macro defines for IRQ register (Interrupt Request Control register)
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**********************************************************************/
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/** I2S control I2S receive interrupt */
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#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
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/** I2S control I2S transmit interrupt */
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#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
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/** I2S set the FIFO level on which to create an irq request */
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#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
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/** I2S set the FIFO level on which to create an irq request */
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#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
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/********************************************************************************//**
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* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
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*********************************************************************************/
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/** I2S Transmit MCLK rate denominator */
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#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
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/** I2S Transmit MCLK rate denominator */
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#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
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/** I2S Receive MCLK rate denominator */
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#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
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/** I2S Receive MCLK rate denominator */
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#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
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/*************************************************************************************//**
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* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
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**************************************************************************************/
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#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
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#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
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/**********************************************************************************//**
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* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
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************************************************************************************/
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/** I2S Transmit select clock source (2 bits)*/
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#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
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/** I2S Transmit control 4-pin mode */
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#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
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/** I2S Transmit control the TX_MCLK output */
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#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
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/** I2S Receive select clock source */
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#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
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/** I2S Receive control 4-pin mode */
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#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
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/** I2S Receive control the TX_MCLK output */
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#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
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/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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/** Macro to determine if it is valid I2S peripheral */
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#define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
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/** Macro to check Data to send valid */
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#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
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/* Macro check I2S word width type */
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#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
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||(n==I2S_WORDWIDTH_32))
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/* Macro check I2S channel type */
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#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
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/* Macro check I2S master/slave mode */
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#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
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/* Macro check I2S stop mode */
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#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
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/* Macro check I2S reset mode */
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#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
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/* Macro check I2S reset mode */
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#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
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/* Macro check I2S transmit/receive mode */
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#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
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/* Macro check I2S clock select mode */
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#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
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/* Macro check I2S 4-pin mode */
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#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
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/* Macro check I2S MCLK mode */
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#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
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/* Macro check I2S DMA mode */
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#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
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/* Macro check I2S DMA depth value */
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#define PARAM_I2S_DMA_DEPTH(n) (n<=31)
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/* Macro check I2S irq level value */
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#define PARAM_I2S_IRQ_LEVEL(n) (n<=31)
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/* Macro check I2S half-period value */
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#define PARAM_I2S_HALFPERIOD(n) (n<512)
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/* Macro check I2S bit-rate value */
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#define PARAM_I2S_BITRATE(n) (n<=63)
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup I2S_Public_Types I2S Public Types
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* @{
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*/
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/**
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* @brief I2S configuration structure definition
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*/
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typedef struct {
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uint8_t wordwidth; /** the number of bytes in data as follow:
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-I2S_WORDWIDTH_8: 8 bit data
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-I2S_WORDWIDTH_16: 16 bit data
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-I2S_WORDWIDTH_32: 32 bit data */
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uint8_t mono; /** Set mono/stereo mode, should be:
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- I2S_STEREO: stereo mode
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- I2S_MONO: mono mode */
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uint8_t stop; /** Disables accesses on FIFOs, should be:
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- I2S_STOP_ENABLE: enable stop mode
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- I2S_STOP_DISABLE: disable stop mode */
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uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
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- I2S_RESET_ENABLE: enable reset mode
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- I2S_RESET_DISABLE: disable reset mode */
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uint8_t ws_sel; /** Set Master/Slave mode, should be:
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- I2S_MASTER_MODE: I2S master mode
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- I2S_SLAVE_MODE: I2S slave mode */
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uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
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- I2S_MUTE_ENABLE: enable mute mode
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- I2S_MUTE_DISABLE: disable mute mode */
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uint8_t Reserved0[2];
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||
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|
} I2S_CFG_Type;
|
||
|
|
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||
|
|
/**
|
||
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|
* @brief I2S DMA configuration structure definition
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
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|
uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
|
||
|
|
- I2S_DMA_1: DMA1
|
||
|
|
- I2S_DMA_2: DMA2 */
|
||
|
|
uint8_t depth; /** FIFO level that triggers a DMA request */
|
||
|
|
uint8_t Reserved0[2];
|
||
|
|
}I2S_DMAConf_Type;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief I2S mode configuration structure definition
|
||
|
|
*/
|
||
|
|
typedef struct{
|
||
|
|
uint8_t clksel; /** Clock source selection, should be:
|
||
|
|
- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
|
||
|
|
- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
|
||
|
|
uint8_t fpin; /** Select four pin mode, should be:
|
||
|
|
- I2S_4PIN_ENABLE: 4-pin enable
|
||
|
|
- I2S_4PIN_DISABLE: 4-pin disable */
|
||
|
|
uint8_t mcena; /** Select MCLK mode, should be:
|
||
|
|
- I2S_MCLK_ENABLE: MCLK enable for output
|
||
|
|
- I2S_MCLK_DISABLE: MCLK disable for output */
|
||
|
|
uint8_t Reserved;
|
||
|
|
}I2S_MODEConf_Type;
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* Public Functions ----------------------------------------------------------- */
|
||
|
|
/** @defgroup I2S_Public_Functions I2S Public Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* I2S Init/DeInit functions ---------*/
|
||
|
|
void I2S_Init(LPC_I2S_TypeDef *I2Sx);
|
||
|
|
void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
|
||
|
|
|
||
|
|
/* I2S configuration functions --------*/
|
||
|
|
void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
|
||
|
|
Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
|
||
|
|
void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
|
||
|
|
void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
|
||
|
|
uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||
|
|
|
||
|
|
/* I2S operate functions -------------*/
|
||
|
|
void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
|
||
|
|
uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
|
||
|
|
void I2S_Start(LPC_I2S_TypeDef *I2Sx);
|
||
|
|
void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||
|
|
void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||
|
|
void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||
|
|
|
||
|
|
/* I2S DMA functions ----------------*/
|
||
|
|
void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
|
||
|
|
void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
|
||
|
|
|
||
|
|
/* I2S IRQ functions ----------------*/
|
||
|
|
void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
|
||
|
|
void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
|
||
|
|
FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
|
||
|
|
uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* LPC17XX_SSP_H_ */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* --------------------------------- End Of File ------------------------------ */
|