302 lines
12 KiB
C
302 lines
12 KiB
C
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/**********************************************************************
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* $Id$ lpc43xx_sdif.h 2012-Aug-15
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*//**
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* @file lpc43xx_sdif.h
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* @brief Contains all macro definitions and function prototypes
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* support for SDIO firmware library on LPC43xx
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* @version 1.0
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* @date 15. Aug. 2012
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup SDIF SDIF (SD Card Interface)
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* @ingroup LPC4300CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC43XX_SDIF_H
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#define LPC43XX_SDIF_H
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#include "LPC43xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup SDIF_Private_Macros SDIF Private Macros
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* @{
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*/
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/** \brief SDIO chained DMA descriptor
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*/
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typedef struct {
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volatile uint32_t des0; /*!< Control and status */
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volatile uint32_t des1; /*!< Buffer size(s) */
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volatile uint32_t des2; /*!< Buffer address pointer 1 */
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volatile uint32_t des3; /*!< Buffer address pointer 2 */
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} LPC_SDMMC_DMA_Type;
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/** \brief SDIO DMA descriptor control (des0) register defines
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*/
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#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */
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#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */
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#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */
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#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */
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#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */
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#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */
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#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */
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/** \brief SDIO DMA descriptor size (des1) register defines
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*/
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#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
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#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
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#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
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/** \brief SDIO control register defines
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*/
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#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */
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#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */
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#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */
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#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */
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#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */
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#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */
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#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */
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#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */
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#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */
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#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */
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#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */
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#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */
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/** \brief SDIO Power Enable register defines
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*/
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#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */
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/** \brief SDIO Clock divider register defines
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*/
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#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */
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/** \brief SDIO Clock source register defines
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*/
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#define MCI_CLKSRC_CLKDIV0 0
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#define MCI_CLKSRC_CLKDIV1 1
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#define MCI_CLKSRC_CLKDIV2 2
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#define MCI_CLKSRC_CLKDIV3 3
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#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */
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/** \brief SDIO Clock Enable register defines
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*/
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#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */
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#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */
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/** \brief SDIO time-out register defines
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*/
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#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */
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#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
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#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
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#define MCI_TMOUT_RESP_MSK 0xFF
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/** \brief SDIO card-type register defines
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*/
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#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */
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#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */
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/** \brief SDIO Interrupt status & mask register defines
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*/
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#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */
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#define MCI_INT_EBE (1 << 15) /*!< End-bit error */
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#define MCI_INT_ACD (1 << 14) /*!< Auto command done */
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#define MCI_INT_SBE (1 << 13) /*!< Start bit error */
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#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */
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#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */
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#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */
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#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */
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#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */
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#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */
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#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */
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#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */
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#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */
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#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */
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#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */
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#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */
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#define MCI_INT_CD (1 << 0) /*!< Card detect */
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/** \brief SDIO Command register defines
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*/
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#define MCI_CMD_START (1UL << 31) /*!< Start command */
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#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */
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#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */
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#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */
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#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */
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#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */
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#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */
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#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */
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#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */
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#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */
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#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */
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#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */
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#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */
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#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */
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#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */
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#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */
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#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */
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#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */
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#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */
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#define MCI_CMD_INDX(n) ((n) & 0x1F)
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/** \brief SDIO status register definess
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*/
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#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
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/** \brief SDIO FIFO threshold defines
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*/
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#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
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#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
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#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
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#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
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#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
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#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
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#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
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#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
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#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
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#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
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/** \brief Bus mode register defines
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*/
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#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */
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#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */
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#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */
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#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */
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#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */
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#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */
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#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */
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#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */
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#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */
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#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */
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#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */
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#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */
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/** \brief Commonly used definitions
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*/
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#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */
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/***********************************************************************
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* MCI device structure and it defines
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**********************************************************************/
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/* Function prototype for SD interface IRQ callback */
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typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
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/* Function prototype for SD detect and write protect status check */
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typedef int32_t (*PSCHECK_FUNC_T) (void);
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/* Function prototype for SD slot power enable or slot reset */
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typedef void (*PS_POWER_FUNC_T) (int32_t enable);
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/* Card specific setup data */
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struct _mci_card_struct
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{
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uint32_t response[4]; /*!< Most recent response */
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uint32_t cid[4]; /*!< CID of acquired card */
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uint32_t csd[4]; /*!< CSD of acquired card */
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uint32_t ext_csd[512 / 4];
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uint32_t card_type;
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uint32_t rca; /*!< Relative address assigned to card */
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uint32_t speed;
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uint32_t block_len;
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uint32_t device_size;
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uint32_t blocknr;
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PSCHECK_FUNC_T sdck_det;
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PSCHECK_FUNC_T sdck_wp;
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PS_POWER_FUNC_T sd_setpow;
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PS_POWER_FUNC_T sd_setrst;
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};
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup SDIO_Public_Functions SDIO Public Functions
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* @{
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*/
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/* Setup DMA descriptors */
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void sdif_dma_setup(uint32_t addr, uint32_t size);
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/* Send a command on the SD bus */
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int32_t sdif_send_cmd(uint32_t cmd, uint32_t arg);
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/* Read the response from the last command */
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void sdif_get_response(uint32_t *resp);
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/* Sets the SD bus clock speed */
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void sdif_set_clock(uint32_t speed);
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/* Detect if an SD card is inserted
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(uses SD_CD pin, returns 0 on card detect) */
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int32_t sdif_card_ndetect(void);
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/* Detect if write protect is enabled
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(uses SD_WP pin, returns 1 if card is write protected) */
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int32_t sdif_card_wp_on(void);
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/* Enable or disable slot power, !0 = enable slot power
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(Uses SD_POW pin, set to high or low based on enable parameter state) */
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void sdif_power_onoff(int32_t enable);
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/* Reset card in slot, must manually de-assert reset after assertion
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(Uses SD_RST pin, set per reset parameter state) */
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void sdif_reset(int32_t reset);
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/* Set block size for transfer */
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void sdif_set_blksize(uint32_t bytes);
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/* Enter or exit low power mode. */
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void sdif_set_lowpower_mode(int32_t lpmode);
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/* Initialize the SD controller */
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void sdif_init(uint32_t sdio_clock, MCI_IRQ_CB_FUNC_T irq_callback);
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/* Close the SD controller */
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void sdif_deinit(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end LPC43XX_SDIF_H */
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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