298 lines
8.8 KiB
ArmAsm
298 lines
8.8 KiB
ArmAsm
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/**************************************************
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*
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* Part one of the system initialization code, contains low-level
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* initialization, plain thumb variant.
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*
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* Copyright 2011 IAR Systems. All rights reserved.
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*
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* $Revision: 50291 $
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*
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**************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD MemManage_Handler
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DCD BusFault_Handler
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DCD UsageFault_Handler
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD DebugMon_Handler
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DCD 0
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD DAC_IRQHandler ; 16 D/A Converter
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DCD M0CORE_IRQHandler ; 17 CortexM0
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DCD DMA_IRQHandler ; 18 General Purpose DMA
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DCD 0 ; 19 Reserved
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DCD 0 ; 20 Reserved
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DCD ETH_IRQHandler ; 21 Ethernet
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DCD SDIO_IRQHandler ; 22 SD/MMC
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DCD LCD_IRQHandler ; 23 LCD
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DCD USB0_IRQHandler ; 24 USB0
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DCD USB1_IRQHandler ; 25 USB1
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DCD SCT_IRQHandler ; 26 State Configurable Timer
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DCD RITIMER_IRQHandler ; 27 Repetitive Interrupt Timer
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DCD TIMER0_IRQHandler ; 28 Timer0
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DCD TIMER1_IRQHandler ; 29 Timer1
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DCD TIMER2_IRQHandler ; 30 Timer2
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DCD TIMER3_IRQHandler ; 31 Timer3
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DCD MCPWM_IRQHandler ; 32 Motor Control PWM
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DCD ADC0_IRQHandler ; 33 A/D Converter 0
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DCD I2C0_IRQHandler ; 34 I2C0
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DCD I2C1_IRQHandler ; 35 I2C1
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DCD SPI_IRQHandler ; 36 Reserved
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DCD ADC1_IRQHandler ; 37 A/D Converter 1
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DCD SSP0_IRQHandler ; 38 SSP0
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DCD SSP1_IRQHandler ; 39 SSP1
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DCD USART0_IRQHandler ; 40 UART0
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DCD UART1_IRQHandler ; 41 UART1
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DCD UART2_IRQHandler ; 42 UART2
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DCD UART3_IRQHandler ; 43 UART3
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DCD I2S0_IRQHandler ; 44 I2S0
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DCD I2S1_IRQHandler ; 45 I2S1
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DCD SPIFI_IRQHandler ; 46 SPIFI
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DCD SGPIO_IRQHandler ; 47 SGPIO
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DCD GPIO0_IRQHandler ; 48 GPIO0
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DCD GPIO1_IRQHandler ; 49 GPIO1
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DCD GPIO2_IRQHandler ; 50 GPIO2
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DCD GPIO3_IRQHandler ; 51 GPIO3
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DCD GPIO4_IRQHandler ; 52 GPIO4
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DCD GPIO5_IRQHandler ; 53 GPIO5
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DCD GPIO6_IRQHandler ; 54 GPIO6
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DCD GPIO7_IRQHandler ; 55 GPIO7
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DCD GINT0_IRQHandler ; 56 GINT0
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DCD GINT1_IRQHandler ; 57 GINT1
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DCD EVENTROUTER_IRQHandler ; 58 Event Router
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DCD C_CAN1_IRQHandler ; 59 CCAN1
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DCD 0
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DCD 0
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DCD ATIMER_IRQHandler ; 62 Alarm Timer
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DCD RTC_IRQHandler ; 63 RTC
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DCD 0
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DCD WWDT_IRQHandler ; 65 WWDT
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DCD 0
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DCD C_CAN0_IRQHandler ; 67 CCAN0
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DCD QEI_IRQHandler ; 68 QEI
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER(2)
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Reset_Handler
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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PUBWEAK HardFault_Handler
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PUBWEAK MemManage_Handler
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PUBWEAK BusFault_Handler
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PUBWEAK UsageFault_Handler
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PUBWEAK SVC_Handler
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PUBWEAK DebugMon_Handler
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PUBWEAK PendSV_Handler
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PUBWEAK SysTick_Handler
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PUBWEAK DAC_IRQHandler
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PUBWEAK M0CORE_IRQHandler
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PUBWEAK DMA_IRQHandler
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PUBWEAK ETH_IRQHandler
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PUBWEAK SDIO_IRQHandler
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PUBWEAK LCD_IRQHandler
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PUBWEAK USB0_IRQHandler
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PUBWEAK USB1_IRQHandler
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PUBWEAK SCT_IRQHandler
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PUBWEAK RITIMER_IRQHandler
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PUBWEAK TIMER0_IRQHandler
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PUBWEAK TIMER1_IRQHandler
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PUBWEAK TIMER2_IRQHandler
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PUBWEAK TIMER3_IRQHandler
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PUBWEAK MCPWM_IRQHandler
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PUBWEAK ADC0_IRQHandler
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PUBWEAK I2C0_IRQHandler
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PUBWEAK I2C1_IRQHandler
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PUBWEAK SPI_IRQHandler
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PUBWEAK ADC1_IRQHandler
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PUBWEAK SSP0_IRQHandler
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PUBWEAK SSP1_IRQHandler
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PUBWEAK USART0_IRQHandler
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PUBWEAK UART1_IRQHandler
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PUBWEAK UART2_IRQHandler
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PUBWEAK UART3_IRQHandler
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PUBWEAK I2S0_IRQHandler
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PUBWEAK I2S1_IRQHandler
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PUBWEAK SPIFI_IRQHandler
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PUBWEAK SGPIO_IRQHandler
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PUBWEAK GPIO0_IRQHandler
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PUBWEAK GPIO1_IRQHandler
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PUBWEAK GPIO2_IRQHandler
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PUBWEAK GPIO3_IRQHandler
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PUBWEAK GPIO4_IRQHandler
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PUBWEAK GPIO5_IRQHandler
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PUBWEAK GPIO6_IRQHandler
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PUBWEAK GPIO7_IRQHandler
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PUBWEAK GINT0_IRQHandler
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PUBWEAK GINT1_IRQHandler
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PUBWEAK EVENTROUTER_IRQHandler
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PUBWEAK C_CAN1_IRQHandler
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PUBWEAK ATIMER_IRQHandler
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PUBWEAK RTC_IRQHandler
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PUBWEAK WWDT_IRQHandler
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PUBWEAK C_CAN0_IRQHandler
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PUBWEAK QEI_IRQHandler
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SECTION .text:CODE:REORDER(1)
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NMI_Handler
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B NMI_Handler
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SVC_Handler
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B SVC_Handler
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DebugMon_Handler
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B DebugMon_Handler
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PendSV_Handler
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B PendSV_Handler
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SysTick_Handler
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B SysTick_Handler
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HardFault_Handler
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B HardFault_Handler
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MemManage_Handler
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B MemManage_Handler
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BusFault_Handler
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B BusFault_Handler
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UsageFault_Handler
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DAC_IRQHandler
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M0CORE_IRQHandler
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DMA_IRQHandler
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ETH_IRQHandler
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SDIO_IRQHandler
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LCD_IRQHandler
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USB0_IRQHandler
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USB1_IRQHandler
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SCT_IRQHandler
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RITIMER_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER3_IRQHandler
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MCPWM_IRQHandler
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ADC0_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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SPI_IRQHandler
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ADC1_IRQHandler
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SSP0_IRQHandler
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SSP1_IRQHandler
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USART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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I2S0_IRQHandler
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I2S1_IRQHandler
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SPIFI_IRQHandler
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SGPIO_IRQHandler
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GPIO0_IRQHandler
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GPIO1_IRQHandler
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GPIO2_IRQHandler
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GPIO3_IRQHandler
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GPIO4_IRQHandler
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GPIO5_IRQHandler
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GPIO6_IRQHandler
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GPIO7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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EVENTROUTER_IRQHandler
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C_CAN1_IRQHandler
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ATIMER_IRQHandler
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RTC_IRQHandler
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WWDT_IRQHandler
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C_CAN0_IRQHandler
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QEI_IRQHandler
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Default_IRQHandler
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B Default_IRQHandler
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THUMB
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PUBLIC getPC
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SECTION .text:CODE:REORDER(2)
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getPC
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MOV R0,LR
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BX LR
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/* CRP Section - not needed for flashless devices */
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;;; SECTION .crp:CODE:ROOT(2)
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;;; DATA
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/* Code Read Protection
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NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
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CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
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- Copy RAM to flash command can not write to Sector 0.
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- Erase command can erase Sector 0 only when all sectors
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are selected for erase.
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- Compare command is disabled.
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- Read Memory command is disabled.
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CRP2 0x87654321 - Read Memory is disabled.
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- Write to RAM is disabled.
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- "Go" command is disabled.
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- Copy RAM to flash is disabled.
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- Compare is disabled.
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CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
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by pulling PIO0_1 LOW is disabled if a valid user code is
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present in flash sector 0.
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Caution: If CRP3 is selected, no future factory testing can be
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performed on the device.
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*/
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;;; DCD 0xFFFFFFFF
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;;;
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END
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