2023-03-17 16:12:49 +07:00
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/*
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2020-01-14 23:30:39 -05:00
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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2024-05-24 14:06:25 +07:00
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#ifndef TUSB_DCD_H_
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#define TUSB_DCD_H_
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2020-01-14 23:30:39 -05:00
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#include "common/tusb_common.h"
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2021-05-27 17:40:39 +07:00
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#include "osal/osal.h"
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2021-01-18 17:08:59 +01:00
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#include "common/tusb_fifo.h"
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2021-07-21 13:21:58 +07:00
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2020-01-14 23:30:39 -05:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-07-21 17:00:02 +07:00
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF PROTYPES
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//--------------------------------------------------------------------+
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2023-11-24 11:38:20 +07:00
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typedef enum {
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2024-07-25 16:49:01 +07:00
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DCD_EVENT_INVALID = 0, // 0
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DCD_EVENT_BUS_RESET, // 1
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DCD_EVENT_UNPLUGGED, // 2
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DCD_EVENT_SOF, // 3
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DCD_EVENT_SUSPEND, // 4 TODO LPM Sleep L1 support
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DCD_EVENT_RESUME, // 5
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DCD_EVENT_SETUP_RECEIVED, // 6
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DCD_EVENT_XFER_COMPLETE, // 7
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USBD_EVENT_FUNC_CALL, // 8 Not an DCD event, just a convenient way to defer ISR function
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2020-01-14 23:30:39 -05:00
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DCD_EVENT_COUNT
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} dcd_eventid_t;
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2023-11-24 11:38:20 +07:00
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typedef struct TU_ATTR_ALIGNED(4) {
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2020-01-14 23:30:39 -05:00
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uint8_t rhport;
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uint8_t event_id;
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2023-11-24 11:38:20 +07:00
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union {
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2020-05-31 23:43:29 +07:00
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// BUS RESET
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struct {
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tusb_speed_t speed;
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} bus_reset;
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2022-03-07 23:03:37 +07:00
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// SOF
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struct {
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uint32_t frame_count;
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}sof;
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2020-05-31 23:43:29 +07:00
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// SETUP_RECEIVED
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2020-01-14 23:30:39 -05:00
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tusb_control_request_t setup_received;
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2020-05-31 23:43:29 +07:00
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// XFER_COMPLETE
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2020-01-14 23:30:39 -05:00
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struct {
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uint8_t ep_addr;
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uint8_t result;
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uint32_t len;
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}xfer_complete;
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2020-10-12 00:35:38 +07:00
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// FUNC_CALL
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2020-01-14 23:30:39 -05:00
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struct {
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void (*func) (void*);
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void* param;
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}func_call;
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};
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} dcd_event_t;
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//TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct");
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2020-09-03 13:12:09 +07:00
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//--------------------------------------------------------------------+
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2023-05-23 21:45:00 +07:00
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// Memory API
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//--------------------------------------------------------------------+
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// clean/flush data cache: write cache -> memory.
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// Required before an DMA TX transfer to make sure data is in memory
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2023-06-16 12:02:42 +07:00
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void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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2023-05-23 21:45:00 +07:00
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// invalidate data cache: mark cache as invalid, next read will read from memory
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// Required BOTH before and after an DMA RX transfer
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2023-06-16 12:02:42 +07:00
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void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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2023-05-23 21:45:00 +07:00
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// clean and invalidate data cache
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// Required before an DMA transfer where memory is both read/write by DMA
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2023-06-16 12:02:42 +07:00
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void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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2023-05-23 21:45:00 +07:00
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//--------------------------------------------------------------------+
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2020-09-03 13:12:09 +07:00
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// Controller API
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//--------------------------------------------------------------------+
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2020-01-14 23:30:39 -05:00
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// Initialize controller to device mode
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2024-10-11 15:21:32 +07:00
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void dcd_init(const tusb_rhport_init_t* rh_init);
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2020-01-14 23:30:39 -05:00
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2023-01-02 17:09:45 +01:00
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// Deinitialize controller, unset device mode.
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2024-04-08 22:07:56 +07:00
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bool dcd_deinit(uint8_t rhport);
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2023-01-02 17:09:45 +01:00
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2020-01-14 23:30:39 -05:00
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// Interrupt Handler
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2020-04-17 12:27:53 +07:00
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void dcd_int_handler(uint8_t rhport);
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2020-01-14 23:30:39 -05:00
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// Enable device interrupt
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void dcd_int_enable (uint8_t rhport);
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// Disable device interrupt
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void dcd_int_disable(uint8_t rhport);
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// Receive Set Address request, mcu port must also include status IN response
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr);
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// Wake up host
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void dcd_remote_wakeup(uint8_t rhport);
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2020-04-16 15:52:45 +07:00
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// Connect by enabling internal pull-up resistor on D+/D-
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2024-05-24 13:58:44 +07:00
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void dcd_connect(uint8_t rhport);
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2020-04-16 15:52:45 +07:00
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// Disconnect by disabling internal pull-up resistor on D+/D-
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2024-05-24 13:58:44 +07:00
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void dcd_disconnect(uint8_t rhport);
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2020-04-09 11:42:42 +07:00
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2022-03-07 23:03:37 +07:00
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// Enable/Disable Start-of-frame interrupt. Default is disabled
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void dcd_sof_enable(uint8_t rhport, bool en);
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2024-05-13 22:26:19 +02:00
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#if CFG_TUD_TEST_MODE
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2024-01-15 12:47:13 +00:00
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// Put device into a test mode (needs power cycle to quit)
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2024-07-12 20:17:14 +07:00
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void dcd_enter_test_mode(uint8_t rhport, tusb_feature_test_mode_t test_selector);
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2024-05-13 22:26:19 +02:00
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#endif
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2020-01-14 23:30:39 -05:00
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//--------------------------------------------------------------------+
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// Endpoint API
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//--------------------------------------------------------------------+
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// Invoked when a control transfer's status stage is complete.
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// May help DCD to prepare for next control transfer, this API is optional.
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2023-08-29 18:16:50 +02:00
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void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request);
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2020-01-14 23:30:39 -05:00
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// Configure endpoint's registers according to descriptor
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2021-06-10 17:19:21 +07:00
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bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
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2020-01-14 23:30:39 -05:00
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2021-08-26 17:02:24 +07:00
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// Close all non-control endpoints, cancel all pending transfers if any.
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// Invoked when switching from a non-zero Configuration by SET_CONFIGURE therefore
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// required for multiple configuration support.
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void dcd_edpt_close_all (uint8_t rhport);
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2020-01-14 23:30:39 -05:00
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// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
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2021-01-31 19:08:23 +01:00
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bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
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2020-01-14 23:30:39 -05:00
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2021-03-10 17:58:39 +07:00
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// Submit an transfer using fifo, When complete dcd_event_xfer_complete() is invoked to notify the stack
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// This API is optional, may be useful for register-based for transferring data.
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bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) TU_ATTR_WEAK;
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2021-01-18 17:08:59 +01:00
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2021-09-01 16:52:27 +07:00
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// Stall endpoint, any queuing transfer should be removed from endpoint
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2021-01-31 19:08:23 +01:00
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void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
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2020-01-14 23:30:39 -05:00
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// clear stall, data toggle is also reset to DATA0
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2021-08-12 00:11:04 +07:00
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// This API never calls with control endpoints, since it is auto cleared when receiving setup packet
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2021-01-31 19:08:23 +01:00
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void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
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2020-01-14 23:30:39 -05:00
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2024-08-19 11:59:41 +07:00
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#ifdef TUP_DCD_EDPT_ISO_ALLOC
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2022-12-29 19:19:27 +01:00
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// Allocate packet buffer used by ISO endpoints
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2023-11-24 11:38:20 +07:00
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// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
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2024-08-19 11:59:41 +07:00
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bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
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2022-12-29 19:19:27 +01:00
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// Configure and enable an ISO endpoint according to descriptor
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2024-08-19 11:59:41 +07:00
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bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
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#else
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// Close an endpoint.
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2024-08-19 20:08:55 +07:00
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void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr);
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2024-08-19 11:59:41 +07:00
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#endif
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2023-06-09 18:15:28 +07:00
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2020-01-14 23:30:39 -05:00
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//--------------------------------------------------------------------+
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2020-09-05 15:45:03 +07:00
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// Event API (implemented by stack)
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2020-01-14 23:30:39 -05:00
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//--------------------------------------------------------------------+
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// Called by DCD to notify device stack
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extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
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// helper to send bus signal event
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2023-11-24 11:38:20 +07:00
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TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) {
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2024-10-11 16:00:51 +07:00
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dcd_event_t event;
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event.rhport = rhport;
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event.event_id = eid;
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2022-04-18 17:49:21 +07:00
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dcd_event_handler(&event, in_isr);
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}
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2020-01-14 23:30:39 -05:00
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2020-05-31 23:43:29 +07:00
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// helper to send bus reset event
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2023-11-24 11:38:20 +07:00
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TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) {
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2024-10-11 16:00:51 +07:00
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dcd_event_t event;
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event.rhport = rhport;
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event.event_id = DCD_EVENT_BUS_RESET;
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2022-04-18 17:49:21 +07:00
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event.bus_reset.speed = speed;
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dcd_event_handler(&event, in_isr);
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}
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2020-05-31 23:43:29 +07:00
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2020-01-14 23:30:39 -05:00
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// helper to send setup received
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2023-11-24 11:38:20 +07:00
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TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) {
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2024-10-11 16:00:51 +07:00
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dcd_event_t event;
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event.rhport = rhport;
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event.event_id = DCD_EVENT_SETUP_RECEIVED;
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2023-01-13 13:37:55 -08:00
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memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t));
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2022-04-18 17:49:21 +07:00
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dcd_event_handler(&event, in_isr);
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}
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2020-01-14 23:30:39 -05:00
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// helper to send transfer complete event
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2023-11-24 11:38:20 +07:00
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TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) {
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2024-10-11 16:00:51 +07:00
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dcd_event_t event;
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event.rhport = rhport;
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event.event_id = DCD_EVENT_XFER_COMPLETE;
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2022-04-18 17:49:21 +07:00
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event.xfer_complete.ep_addr = ep_addr;
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event.xfer_complete.len = xferred_bytes;
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event.xfer_complete.result = result;
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dcd_event_handler(&event, in_isr);
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}
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2020-01-14 23:30:39 -05:00
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2023-11-24 11:38:20 +07:00
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TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) {
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2024-10-11 16:00:51 +07:00
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dcd_event_t event;
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event.rhport = rhport;
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event.event_id = DCD_EVENT_SOF;
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2022-03-07 23:03:37 +07:00
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event.sof.frame_count = frame_count;
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dcd_event_handler(&event, in_isr);
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}
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2020-01-14 23:30:39 -05:00
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#ifdef __cplusplus
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}
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#endif
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2024-05-24 14:06:25 +07:00
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#endif
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