merge saml21 + saml22 = saml2x
This commit is contained in:
hathach
50
hw/bsp/saml2x/boards/atsaml21_xpro/board.h
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50
hw/bsp/saml2x/boards/atsaml21_xpro/board.h
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@@ -0,0 +1,50 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// LED
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#define LED_PIN (32 + 30) // PB30
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#define LED_STATE_ON 0
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// Button
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#define BUTTON_PIN (0 + 15) // PA15
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#define BUTTON_STATE_ACTIVE 0
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// UART
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#define UART_RX_PIN 4
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#define UART_TX_PIN 5
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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12
hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
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12
hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
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@@ -0,0 +1,12 @@
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CFLAGS += -D__SAML21J18B__
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SAML_VARIANT = saml21
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/saml21j18b_flash.ld
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# For flash-jlink target
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JLINK_DEVICE = ATSAML21J18
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# flash using jlink
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flash: flash-jlink
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153
hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
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153
hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
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@@ -0,0 +1,153 @@
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/**
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* \file
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*
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* \brief Linker script for running in internal FLASH on the SAML21J18B
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*
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* Copyright (c) 2016 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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SEARCH_DIR(.)
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/* Memory Spaces Definitions */
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MEMORY
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{
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rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
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lpram (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000
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}
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/* The stack size used by the application. NOTE: you need to adjust according to your application. */
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STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
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/* Section Definitions */
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SECTIONS
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{
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.text :
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{
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. = ALIGN(4);
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_sfixed = .;
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KEEP(*(.vectors .vectors.*))
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*(.text .text.* .gnu.linkonce.t.*)
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*(.glue_7t) *(.glue_7)
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*(.rodata .rodata* .gnu.linkonce.r.*)
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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/* Support C constructors, and C destructors in both user code
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and the C library. This also provides support for C++ code. */
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. = ALIGN(4);
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KEEP(*(.init))
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. = ALIGN(4);
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__preinit_array_start = .;
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KEEP (*(.preinit_array))
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__preinit_array_end = .;
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. = ALIGN(4);
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__init_array_end = .;
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. = ALIGN(4);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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. = ALIGN(4);
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_efixed = .; /* End of text section */
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} > rom
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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PROVIDE_HIDDEN (__exidx_start = .);
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > rom
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PROVIDE_HIDDEN (__exidx_end = .);
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. = ALIGN(4);
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_etext = .;
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.relocate : AT (_etext)
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{
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. = ALIGN(4);
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_srelocate = .;
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*(.ramfunc .ramfunc.*);
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*(.data .data.*);
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. = ALIGN(4);
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_erelocate = .;
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} > ram
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.lpram (NOLOAD):
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{
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. = ALIGN(8);
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_slpram = .;
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*(.lpram .lpram.*);
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. = ALIGN(8);
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_elpram = .;
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} > lpram
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/* .bss section which is used for uninitialized data */
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_sbss = . ;
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_szero = .;
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = . ;
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_ezero = .;
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end = .;
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} > ram
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/* stack section */
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.stack (NOLOAD):
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{
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. = ALIGN(8);
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_sstack = .;
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. = . + STACK_SIZE;
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. = ALIGN(8);
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_estack = .;
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} > ram
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. = ALIGN(4);
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_end = . ;
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}
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@@ -1,5 +1,7 @@
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CFLAGS += -D__SAML22J18A__
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SAML_VARIANT = saml22
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/$(BOARD).ld
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@@ -1,5 +1,7 @@
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CFLAGS += -D__SAML22J18A__
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SAML_VARIANT = saml22
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/$(BOARD).ld
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@@ -108,13 +108,13 @@ void board_init(void)
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gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
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// Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
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hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
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TCC0->PER.bit.PER = 48000000 / 1000;
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TCC0->CC[3].bit.CC = 48000000 / 2000;
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TCC0->CTRLA.bit.ENABLE = true;
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gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
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hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
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// hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
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// TCC0->PER.bit.PER = 48000000 / 1000;
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// TCC0->CC[3].bit.CC = 48000000 / 2000;
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// TCC0->CTRLA.bit.ENABLE = true;
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//
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// gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
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// hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
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}
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//--------------------------------------------------------------------+
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@@ -1,8 +1,10 @@
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UF2_FAMILY_ID = 0x68ed2b88
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DEPS_SUBMODULES += hw/mcu/microchip
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DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
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include $(TOP)/$(BOARD_PATH)/board.mk
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MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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@@ -13,29 +15,25 @@ CFLAGS += \
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SRC_C += \
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src/portable/microchip/samd/dcd_samd.c \
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hw/mcu/microchip/saml22/gcc/gcc/startup_saml22.c \
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hw/mcu/microchip/saml22/gcc/system_saml22.c \
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hw/mcu/microchip/saml22/hpl/gclk/hpl_gclk.c \
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hw/mcu/microchip/saml22/hpl/mclk/hpl_mclk.c \
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hw/mcu/microchip/saml22/hpl/pm/hpl_pm.c \
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hw/mcu/microchip/saml22/hpl/osc32kctrl/hpl_osc32kctrl.c \
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hw/mcu/microchip/saml22/hpl/oscctrl/hpl_oscctrl.c \
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hw/mcu/microchip/saml22/hal/src/hal_atomic.c
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$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
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$(MCU_DIR)/gcc/system_$(SAML_VARIANT).c \
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$(MCU_DIR)/hpl/gclk/hpl_gclk.c \
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$(MCU_DIR)/hpl/mclk/hpl_mclk.c \
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$(MCU_DIR)/hpl/pm/hpl_pm.c \
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$(MCU_DIR)/hpl/osc32kctrl/hpl_osc32kctrl.c \
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$(MCU_DIR)/hpl/oscctrl/hpl_oscctrl.c \
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$(MCU_DIR)/hal/src/hal_atomic.c
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INC += \
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$(TOP)/$(BOARD_PATH) \
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$(TOP)/hw/mcu/microchip/saml22/ \
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$(TOP)/hw/mcu/microchip/saml22/config \
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$(TOP)/hw/mcu/microchip/saml22/include \
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$(TOP)/hw/mcu/microchip/saml22/hal/include \
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$(TOP)/hw/mcu/microchip/saml22/hal/utils/include \
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$(TOP)/hw/mcu/microchip/saml22/hpl/port \
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$(TOP)/hw/mcu/microchip/saml22/hri \
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$(TOP)/hw/mcu/microchip/saml22/CMSIS/Core/Include
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# For TinyUSB port source
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VENDOR = microchip
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CHIP_FAMILY = samd
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$(TOP)/$(MCU_DIR)/ \
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$(TOP)/$(MCU_DIR)/config \
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$(TOP)/$(MCU_DIR)/include \
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$(TOP)/$(MCU_DIR)/hal/include \
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$(TOP)/$(MCU_DIR)/hal/utils/include \
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$(TOP)/$(MCU_DIR)/hpl/port \
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$(TOP)/$(MCU_DIR)/hri \
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$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM0
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