more progress on dwc2 hcd, initial code for edpt xfer
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@@ -168,16 +168,16 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
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//--------------------------------------------------------------------
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//
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//--------------------------------------------------------------------
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bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
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bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
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(void)dwc2;
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#if CFG_TUD_ENABLED
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if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
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if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
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return false;
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}
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#endif
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#if CFG_TUH_ENABLED
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if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
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if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) {
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return false;
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}
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#endif
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@@ -234,15 +234,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
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dwc2->gintmsk = 0;
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// TODO can be enabled with device as well but tested with host for now
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// if (rh_init->role == TUSB_ROLE_HOST) {
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// dwc2->gintmsk |= OTG_INT_COMMON;
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// }
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if (is_dma) {
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const uint16_t epinfo_base = dma_cal_epfifo_base(rhport);
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dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base;
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// DMA seems to be only settable after a core reset, and not possible to switch on-the-fly
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dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
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} else {
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