diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake new file mode 100644 index 000000000..9dc6962eb --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.cmake @@ -0,0 +1 @@ +# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h new file mode 100644 index 000000000..f94097ca9 --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_1 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 1 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_27 +#define BUTTON_PULL MXC_GPIO_PAD_NONE +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for UART on ARM SWD Connector +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk new file mode 100644 index 000000000..a813a5327 --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.mk @@ -0,0 +1 @@ +# No specific build requirements for the board. diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h index f5a904702..05d60f220 100644 --- a/hw/bsp/max32690/boards/max32690evkit/board.h +++ b/hw/bsp/max32690/boards/max32690evkit/board.h @@ -31,26 +31,26 @@ #include "mxc_sys.h" #ifdef __cplusplus - extern "C" { +extern "C" { #endif // LED -#define LED_PORT MXC_GPIO0 -#define LED_PIN MXC_GPIO_PIN_14 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 +#define LED_PORT MXC_GPIO0 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 // Button -#define BUTTON_PORT MXC_GPIO4 -#define BUTTON_PIN MXC_GPIO_PIN_0 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_PORT MXC_GPIO4 +#define BUTTON_PIN MXC_GPIO_PIN_0 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 // UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 2 +#define UART_NUM 2 #ifdef __cplusplus - } +} #endif #endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index f443bc575..acd6e2593 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -24,12 +24,12 @@ * This file is part of the TinyUSB stack. */ -#include "bsp/board_api.h" #include "board.h" -#include "mxc_device.h" -#include "mcr_regs.h" -#include "uart.h" +#include "bsp/board_api.h" #include "gpio.h" +#include "mcr_regs.h" +#include "mxc_device.h" +#include "uart.h" //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler @@ -49,7 +49,7 @@ void board_init(void) { SysTick_Config(SystemCoreClock / 1000); #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif mxc_gpio_cfg_t gpioConfig; @@ -87,10 +87,10 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - #if LED_STATE_ON - state = !state; - #endif - if(state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { MXC_GPIO_OutClr(LED_PORT, LED_PIN); } else { MXC_GPIO_OutSet(LED_PORT, LED_PIN); @@ -103,9 +103,9 @@ uint32_t board_button_read(void) { } size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer - /* All other 2nd parameter is optional checkum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); memcpy(id, hw_id, act_len); @@ -116,11 +116,11 @@ int board_uart_read(uint8_t *buf, int len) { int uart_val; int act_len = 0; - while( act_len < len ) { - if((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { break; } else { - *buf++ = (uint8_t)uart_val; + *buf++ = (uint8_t) uart_val; act_len++; } } @@ -129,8 +129,8 @@ int board_uart_read(uint8_t *buf, int len) { int board_uart_write(void const *buf, int len) { int act_len = 0; - const uint8_t* ch_ptr = (const uint8_t*)buf; - while(act_len < len){ + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); act_len++; } diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index 150d476fa..b3370ddd1 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -29,49 +29,48 @@ #if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) -#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) + #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though * the target CPU has the capability for unaligned memory access. */ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); -#endif + #endif -#include "device/dcd.h" + #include "device/dcd.h" -#include "mxc_delay.h" -#include "mxc_device.h" -#include "mxc_sys.h" -#include "nvic_table.h" -#include "usbhs_regs.h" + #include "mxc_delay.h" + #include "mxc_device.h" + #include "mxc_sys.h" + #include "nvic_table.h" + #include "usbhs_regs.h" -#define USBHS_M31_CLOCK_RECOVERY + #define USBHS_M31_CLOCK_RECOVERY -/*------------------------------------------------------------------ + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ -#define REQUEST_TYPE_INVALID (0xFFu) + #define REQUEST_TYPE_INVALID (0xFFu) typedef union { - uint8_t u8; - uint16_t u16; - uint32_t u32; + uint8_t u8; + uint16_t u16; + uint32_t u32; } hw_fifo_t; -typedef struct TU_ATTR_PACKED -{ - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ +typedef struct TU_ATTR_PACKED { + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ } pipe_state_t; typedef struct { tusb_control_request_t setup_packet; - uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ - int8_t status_out; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; pipe_state_t pipe0; - pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ - uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; /*------------------------------------------------------------------ @@ -80,63 +79,59 @@ typedef struct static dcd_data_t _dcd; -static volatile void* edpt_get_fifo_ptr(unsigned epnum) -{ - volatile uint32_t *ptr; +static volatile void *edpt_get_fifo_ptr(unsigned epnum) { + volatile uint32_t *ptr; - ptr = &MXC_USBHS->fifo0; - ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ + ptr = &MXC_USBHS->fifo0; + ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ - return (volatile void *)ptr; + return (volatile void *) ptr; } -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { + volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; + uintptr_t addr = (uintptr_t) buf; while (len >= 4) { - reg->u32 = *(uint32_t const *)addr; + reg->u32 = *(uint32_t const *) addr; addr += 4; - len -= 4; + len -= 4; } if (len >= 2) { - reg->u16 = *(uint16_t const *)addr; + reg->u16 = *(uint16_t const *) addr; addr += 2; - len -= 2; + len -= 2; } if (len) { - reg->u8 = *(uint8_t const *)addr; + reg->u8 = *(uint8_t const *) addr; } } -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { + volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; + uintptr_t addr = (uintptr_t) buf; while (len >= 4) { - *(uint32_t *)addr = reg->u32; + *(uint32_t *) addr = reg->u32; addr += 4; - len -= 4; + len -= 4; } if (len >= 2) { - *(uint16_t *)addr = reg->u16; + *(uint16_t *) addr = reg->u16; addr += 2; - len -= 2; + len -= 2; } if (len) { - *(uint8_t *)addr = reg->u8; + *(uint8_t *) addr = reg->u8; } } -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) { static const struct { void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + /* OUT */ {tu_fifo_get_write_info, tu_fifo_advance_write_pointer, pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, }; tu_fifo_buffer_info_t info; ops[dir].tu_fifo_get_info(f, &info); @@ -152,19 +147,18 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne ops[dir].tu_fifo_advance(f, total_len - rem); } -static void process_setup_packet(uint8_t rhport) -{ - uint32_t *p = (void*)&_dcd.setup_packet; - p[0] = MXC_USBHS->fifo0; - p[1] = MXC_USBHS->fifo0; +static void process_setup_packet(uint8_t rhport) { + uint32_t *p = (void *) &_dcd.setup_packet; + p[0] = MXC_USBHS->fifo0; + p[1] = MXC_USBHS->fifo0; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; - dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + dcd_event_setup_received(rhport, (const uint8_t *) (uintptr_t) &_dcd.setup_packet, true); - const unsigned len = _dcd.setup_packet.wLength; - _dcd.remaining_ctrl = len; + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); /* Clear RX FIFO and reverse the transaction direction */ if (len && dir_in) { @@ -173,12 +167,11 @@ static void process_setup_packet(uint8_t rhport) } } -static bool handle_xfer_in(uint_fast8_t ep_addr) -{ +static bool handle_xfer_in(uint_fast8_t ep_addr) { unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - const unsigned rem = pipe->remaining; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; //This function should not be for ep0 TU_ASSERT(epnum); @@ -191,28 +184,26 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) MXC_USBHS->index = epnum; const unsigned mps = MXC_USBHS->inmaxp; const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); - // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); + void *buf = pipe->buf; + volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf,fifo_ptr, len); - pipe->buf = buf + len; + pipe_write_packet(buf, fifo_ptr, len); + pipe->buf = buf + len; } pipe->remaining = rem - len; } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY; //TODO: Verify a | isnt needed + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isnt needed return false; } -static bool handle_xfer_out(uint_fast8_t ep_addr) -{ +static bool handle_xfer_out(uint_fast8_t ep_addr) { unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; //This function should not be for ep0 TU_ASSERT(epnum); @@ -225,14 +216,14 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) const unsigned rem = pipe->remaining; const unsigned vld = MXC_USBHS->outcount; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + void *buf = pipe->buf; + volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf,fifo_ptr, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); } else { pipe_read_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; + pipe->buf = buf + len; } pipe->remaining = rem - len; } @@ -240,37 +231,35 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) pipe->buf = NULL; return NULL != buf; } - MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit */ //TODO: Verify just setting to 0 is ok + MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit *///TODO: Verify just setting to 0 is ok return false; } -static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; - unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - unsigned dir_in = tu_edpt_dir(ep_addr); + unsigned dir_in = tu_edpt_dir(ep_addr); pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; if (dir_in) { handle_xfer_in(ep_addr); } else { MXC_USBHS->index = epnum; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY){ - MXC_USBHS->outcsrl = 0; //TODO: Verify just setting to 0 is ok + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = 0;//TODO: Verify just setting to 0 is ok } } return true; } -static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ const unsigned req = _dcd.setup_packet.bmRequestType; @@ -299,15 +288,15 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); const unsigned rem = _dcd.remaining_ctrl; const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); - volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + volatile void *fifo_ptr = edpt_get_fifo_ptr(0); if (dir_in) { pipe_write_packet(buffer, fifo_ptr, len); - _dcd.pipe0.buf = buffer + len; - _dcd.pipe0.length = len; + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; _dcd.pipe0.remaining = 0; - _dcd.remaining_ctrl = rem - len; + _dcd.remaining_ctrl = rem - len; if ((len < 64) || (rem == len)) { _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; @@ -317,14 +306,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ } } else { - _dcd.pipe0.buf = buffer; - _dcd.pipe0.length = len; + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; @@ -332,8 +321,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ return true; } -static void process_ep0(uint8_t rhport) -{ +static void process_ep0(uint8_t rhport) { MXC_USBHS->index = 0; uint_fast8_t csrl = MXC_USBHS->csr0; @@ -364,7 +352,7 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0,); + TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0, ); process_setup_packet(rhport); return; } @@ -373,7 +361,7 @@ static void process_ep0(uint8_t rhport) const unsigned vld = MXC_USBHS->count0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + volatile void *fifo_ptr = edpt_get_fifo_ptr(0); pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); _dcd.pipe0.remaining = rem - len; @@ -392,9 +380,9 @@ static void process_ep0(uint8_t rhport) * or receiving a zero length packet. */ if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { /* STATUS IN */ - if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + if (*(const uint16_t *) (uintptr_t) &_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - MXC_USBHS->faddr = (uint8_t)_dcd.setup_packet.wValue; + MXC_USBHS->faddr = (uint8_t) _dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -413,11 +401,10 @@ static void process_ep0(uint8_t rhport) } } -static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) -{ +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { bool completed; - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epnum = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epnum = tu_edpt_number(ep_addr); MXC_USBHS->index = epnum; @@ -443,10 +430,8 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) } } -static void process_bus_reset(uint8_t rhport) -{ - (void)rhport; - TU_LOG0("------Bus Reset\r\n"); +static void process_bus_reset(uint8_t rhport) { + (void) rhport; /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -462,14 +447,14 @@ static void process_bus_reset(uint8_t rhport) for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { MXC_USBHS->index = i; if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; - } + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; + } - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } } dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } @@ -478,9 +463,8 @@ static void process_bus_reset(uint8_t rhport) * Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ - (void)rhport; +void dcd_init(uint8_t rhport) { + (void) rhport; MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; //Interrupt for VBUS disconnect @@ -495,17 +479,17 @@ void dcd_init(uint8_t rhport) /* Configure PHY */ MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); MXC_USBHS->m31_phy_xcfgi_63_32 = 0; - MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72-64); + MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); MXC_USBHS->m31_phy_xcfgi_127_96 = 0; -#ifdef USBHS_M31_CLOCK_RECOVERY + #ifdef USBHS_M31_CLOCK_RECOVERY MXC_USBHS->m31_phy_noncry_rstb = 1; MXC_USBHS->m31_phy_noncry_en = 1; MXC_USBHS->m31_phy_outclksel = 0; MXC_USBHS->m31_phy_coreclkin = 0; MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ -#else + #else /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ /* As it depends on the system core clock, this should probably be done at the SYS level */ MXC_USBHS->m31_phy_noncry_rstb = 0; @@ -513,7 +497,7 @@ void dcd_init(uint8_t rhport) MXC_USBHS->m31_phy_outclksel = 1; MXC_USBHS->m31_phy_coreclkin = 1; MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ -#endif + #endif MXC_USBHS->m31_phy_pll_en = 1; MXC_USBHS->m31_phy_oscouten = 1; @@ -524,25 +508,22 @@ void dcd_init(uint8_t rhport) dcd_connect(rhport); } -void dcd_int_enable(uint8_t rhport) -{ - (void)rhport; +void dcd_int_enable(uint8_t rhport) { + (void) rhport; NVIC_EnableIRQ(USB_IRQn); } -void dcd_int_disable(uint8_t rhport) -{ - (void)rhport; +void dcd_int_disable(uint8_t rhport) { + (void) rhport; NVIC_DisableIRQ(USB_IRQn); } // Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ MXC_USBHS->index = 0; @@ -550,37 +531,33 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) } // Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; +void dcd_remote_wakeup(uint8_t rhport) { + (void) rhport; MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; -#if CFG_TUSB_OS != OPT_OS_NONE + #if CFG_TUSB_OS != OPT_OS_NONE osal_task_delay(10); -#else + #else MXC_Delay(MXC_DELAY_MSEC(10)); -#endif + #endif MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) -{ - (void)rhport; +void dcd_connect(uint8_t rhport) { + (void) rhport; MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; +void dcd_disconnect(uint8_t rhport) { + (void) rhport; MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; } -void dcd_sof_enable(uint8_t rhport, bool en) -{ +void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; (void) en; @@ -592,21 +569,20 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) { (void) rhport; const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - const unsigned mps = tu_edpt_packet_size(ep_desc); + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; - pipe->buf = NULL; - pipe->length = 0; + pipe->buf = NULL; + pipe->length = 0; pipe->remaining = 0; MXC_USBHS->index = epn; @@ -634,8 +610,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } -void dcd_edpt_close_all(uint8_t rhport) -{ +void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; MXC_SYS_Crit_Enter(); @@ -665,10 +640,9 @@ void dcd_edpt_close_all(uint8_t rhport) MXC_SYS_Crit_Exit(); } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - unsigned const epn = tu_edpt_number(ep_addr); +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); MXC_SYS_Crit_Enter(); @@ -683,7 +657,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; } } else { - MXC_USBHS->introuten &= ~TU_BIT(epn); + MXC_USBHS->introuten &= ~TU_BIT(epn); MXC_USBHS->outmaxp = 0; MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { @@ -696,9 +670,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - (void)rhport; +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; bool ret; unsigned const epnum = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); @@ -712,23 +685,21 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t } // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - (void)rhport; +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { + (void) rhport; bool ret; unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); MXC_SYS_Crit_Enter(); _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t *) ff, total_bytes); MXC_SYS_Crit_Exit(); return ret; } // Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; unsigned const epn = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); MXC_USBHS->index = epn; @@ -742,7 +713,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) if (tu_edpt_dir(ep_addr)) { /* IN */ MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; } else { /* OUT */ - TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY),); + TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY), ); MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; } } @@ -750,9 +721,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) } // clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; unsigned const epn = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); MXC_USBHS->index = epn; @@ -779,8 +749,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------- * ISR *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) -{ +void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; uint32_t mxm_int, mxm_int_en, mxm_is; uint32_t saved_index; @@ -788,7 +757,7 @@ void dcd_int_handler(uint8_t rhport) /* Save current index register */ saved_index = MXC_USBHS->index; - is = MXC_USBHS->intrusb; /* read and clear interrupt status */ + is = MXC_USBHS->intrusb; /* read and clear interrupt status */ txis = MXC_USBHS->intrin; /* read and clear interrupt status */ rxis = MXC_USBHS->introut; /* read and clear interrupt status */