From 0d9a24c416cce6fc7201d9201dc131ec2b2110c3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 30 Nov 2024 23:18:22 +0100
Subject: [PATCH] Fix HCD build.

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h |  6 +++---
 src/portable/chipidea/ci_hs/dcd_ci_hs.c   | 14 ++++++++++++++
 src/portable/chipidea/ci_hs/hcd_ci_hs.c   |  2 ++
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index c53556f79..75d1d55b8 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -77,7 +77,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
   return !(0x20000000 <= addr && addr < 0x20100000);
 }
 
-bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
     TU_ASSERT(tu_is_aligned32(addr32));
@@ -87,7 +87,7 @@ bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
   return true;
 }
 
-bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
     // Invalidating does not push cached changes back to RAM so we need to be
@@ -100,7 +100,7 @@ bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
   return true;
 }
 
-bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
     TU_ASSERT(tu_is_aligned32(addr32));
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 331fbfe80..a716dc24c 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -34,6 +34,20 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
 
+#if CFG_TUD_MEM_DCACHE_ENABLE
+bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean(addr, data_size);
+}
+
+bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_invalidate(addr, data_size);
+}
+
+bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean_invalidate(addr, data_size);
+}
+#endif
+
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
 
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 14f8acb45..c4c342a70 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -42,6 +42,7 @@
 
 #include "ci_hs_imxrt.h"
 
+#if CFG_TUH_MEM_DCACHE_ENABLE
 bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
   return imxrt_dcache_clean(addr, data_size);
 }
@@ -53,6 +54,7 @@ bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
 bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
   return imxrt_dcache_clean_invalidate(addr, data_size);
 }
+#endif
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)