andy/tinyUSB
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fix HCD build.

Browse Source 
Signed-off-by: HiFiPhile <admin@hifiphile.com>
This commit is contained in:
HiFiPhile
2024-11-30 23:18:22 +01:00
parent f934224351
commit 0d9a24c416
3 changed files with 19 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/portable/chipidea/ci_hs/ci_hs_imxrt.h
View File

@@ -77,7 +77,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
return !(0x20000000 <= addr && addr < 0x20100000); return !(0x20000000 <= addr && addr < 0x20100000);
} }
bool dcd_dcache_clean(void const* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr; const uintptr_t addr32 = (uintptr_t) addr;
if (imxrt_is_cache_mem(addr32)) { if (imxrt_is_cache_mem(addr32)) {
TU_ASSERT(tu_is_aligned32(addr32)); TU_ASSERT(tu_is_aligned32(addr32));
@@ -87,7 +87,7 @@ bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
return true; return true;
} }
bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr; const uintptr_t addr32 = (uintptr_t) addr;
if (imxrt_is_cache_mem(addr32)) { if (imxrt_is_cache_mem(addr32)) {
// Invalidating does not push cached changes back to RAM so we need to be // Invalidating does not push cached changes back to RAM so we need to be
@@ -100,7 +100,7 @@ bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
return true; return true;
} }
bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
const uintptr_t addr32 = (uintptr_t) addr; const uintptr_t addr32 = (uintptr_t) addr;
if (imxrt_is_cache_mem(addr32)) { if (imxrt_is_cache_mem(addr32)) {
TU_ASSERT(tu_is_aligned32(addr32)); TU_ASSERT(tu_is_aligned32(addr32));

14
src/portable/chipidea/ci_hs/dcd_ci_hs.c
View File

@@ -34,6 +34,20 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
#include "ci_hs_imxrt.h" #include "ci_hs_imxrt.h"
#if CFG_TUD_MEM_DCACHE_ENABLE
bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean(addr, data_size);
}
bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_invalidate(addr, data_size);
}
bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean_invalidate(addr, data_size);
}
#endif
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h" #include "ci_hs_lpc18_43.h"

2
src/portable/chipidea/ci_hs/hcd_ci_hs.c
View File

@@ -42,6 +42,7 @@
#include "ci_hs_imxrt.h" #include "ci_hs_imxrt.h"
#if CFG_TUH_MEM_DCACHE_ENABLE
bool hcd_dcache_clean(void const* addr, uint32_t data_size) { bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean(addr, data_size); return imxrt_dcache_clean(addr, data_size);
} }
@@ -53,6 +54,7 @@ bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean_invalidate(addr, data_size); return imxrt_dcache_clean_invalidate(addr, data_size);
} }
#endif
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)