able to build lpc11u with IAR
clean ending warming with IAR
This commit is contained in:
hathach
File diff suppressed because it is too large
Load Diff
@@ -1,64 +1,64 @@
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC11Uxx software example
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||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for GPIO.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __GPIO_H
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#define __GPIO_H
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||||
|
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#define CHANNEL0 0
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#define CHANNEL1 1
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#define CHANNEL2 2
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#define CHANNEL3 3
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#define CHANNEL4 4
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#define CHANNEL5 5
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#define CHANNEL6 6
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#define CHANNEL7 7
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#define PORT0 0
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#define PORT1 1
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#define GROUP0 0
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#define GROUP1 1
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void FLEX_INT0_IRQHandler(void);
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void FLEX_INT1_IRQHandler(void);
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void FLEX_INT2_IRQHandler(void);
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void FLEX_INT3_IRQHandler(void);
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void FLEX_INT4_IRQHandler(void);
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void FLEX_INT5_IRQHandler(void);
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void FLEX_INT6_IRQHandler(void);
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void FLEX_INT7_IRQHandler(void);
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void GINT0_IRQHandler(void);
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void GINT1_IRQHandler(void);
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void GPIOInit( void );
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void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
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uint32_t sense, uint32_t event );
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void GPIOFlexIntEnable( uint32_t channelNum, uint32_t event );
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void GPIOFlexIntDisable( uint32_t channelNum, uint32_t event );
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uint32_t GPIOFlexIntStatus( uint32_t channelNum );
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void GPIOFlexIntClear( uint32_t channelNum );
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void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
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uint32_t sense, uint32_t *eventPattern );
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uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
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void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
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void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
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#endif /* end __GPIO_H */
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/*****************************************************************************
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** End Of File
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******************************************************************************/
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||||
/****************************************************************************
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||||
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
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||||
* Project: NXP LPC11Uxx software example
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||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for GPIO.
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||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
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****************************************************************************/
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#ifndef __GPIO_H
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#define __GPIO_H
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#define CHANNEL0 0
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#define CHANNEL1 1
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#define CHANNEL2 2
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#define CHANNEL3 3
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#define CHANNEL4 4
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#define CHANNEL5 5
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#define CHANNEL6 6
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#define CHANNEL7 7
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#define PORT0 0
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#define PORT1 1
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#define GROUP0 0
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#define GROUP1 1
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void FLEX_INT0_IRQHandler(void);
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void FLEX_INT1_IRQHandler(void);
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void FLEX_INT2_IRQHandler(void);
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void FLEX_INT3_IRQHandler(void);
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void FLEX_INT4_IRQHandler(void);
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void FLEX_INT5_IRQHandler(void);
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void FLEX_INT6_IRQHandler(void);
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void FLEX_INT7_IRQHandler(void);
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void GINT0_IRQHandler(void);
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void GINT1_IRQHandler(void);
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void GPIOInit( void );
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void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
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uint32_t sense, uint32_t event );
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void GPIOFlexIntEnable( uint32_t channelNum, uint32_t event );
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void GPIOFlexIntDisable( uint32_t channelNum, uint32_t event );
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uint32_t GPIOFlexIntStatus( uint32_t channelNum );
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void GPIOFlexIntClear( uint32_t channelNum );
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void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
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uint32_t sense, uint32_t *eventPattern );
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uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
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void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
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void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
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#endif /* end __GPIO_H */
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/*****************************************************************************
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** End Of File
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******************************************************************************/
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@@ -1,238 +1,238 @@
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/*****************************************************************************
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* uart.c: UART API file for NXP LPC11xx Family Microprocessors
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*
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* Copyright(C) 2008, NXP Semiconductor
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* All rights reserved.
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||||
*
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||||
* History
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* 2009.12.07 ver 1.00 Preliminary version, first Release
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*
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******************************************************************************/
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#include <stdint.h>
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#include "LPC11Uxx.h"
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#include "lpc11uxx_uart.h"
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volatile uint32_t UARTStatus;
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volatile uint8_t UARTTxEmpty = 1;
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volatile uint8_t UARTBuffer[BUFSIZE];
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volatile uint32_t UARTCount = 0;
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/*****************************************************************************
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** Function name: UART_IRQHandler
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**
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** Descriptions: UART interrupt handler
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**
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** parameters: None
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** Returned value: None
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||||
**
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*****************************************************************************/
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void UART_IRQHandler(void)
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{
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uint8_t IIRValue, LSRValue;
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uint8_t Dummy = Dummy;
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IIRValue = LPC_USART->IIR;
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IIRValue >>= 1; /* skip pending bit in IIR */
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
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if (IIRValue == IIR_RLS) /* Receive Line Status */
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{
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LSRValue = LPC_USART->LSR;
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/* Receive Line Status */
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if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
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{
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/* There are errors or break interrupt */
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/* Read LSR will clear the interrupt */
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UARTStatus = LSRValue;
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Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
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interrupt, then bail out */
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return;
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}
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if (LSRValue & LSR_RDR) /* Receive Data Ready */
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{
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/* If no error on RLS, normal ready, save into the data buffer. */
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/* Note: read RBR will clear the interrupt */
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UARTBuffer[UARTCount++] = LPC_USART->RBR;
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if (UARTCount == BUFSIZE)
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{
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UARTCount = 0; /* buffer overflow */
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}
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}
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}
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else if (IIRValue == IIR_RDA) /* Receive Data Available */
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{
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/* Receive Data Available */
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UARTBuffer[UARTCount++] = LPC_USART->RBR;
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if (UARTCount == BUFSIZE)
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{
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UARTCount = 0; /* buffer overflow */
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}
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||||
}
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else if (IIRValue == IIR_CTI) /* Character timeout indicator */
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{
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/* Character Time-out indicator */
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UARTStatus |= 0x100; /* Bit 9 as the CTI error */
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}
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else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
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{
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/* THRE interrupt */
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LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
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valid data in U0THR or not */
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if (LSRValue & LSR_THRE)
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{
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UARTTxEmpty = 1;
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}
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else
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{
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UARTTxEmpty = 0;
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}
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}
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return;
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}
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#if MODEM_TEST
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/*****************************************************************************
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** Function name: ModemInit
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**
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** Descriptions: Initialize UART0 port as modem, setup pin select.
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**
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** parameters: None
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||||
** Returned value: None
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**
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*****************************************************************************/
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void ModemInit( void )
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{
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LPC_IOCON->PIO2_0 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO2_0 |= 0x01; /* UART DTR */
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LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
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LPC_IOCON->PIO1_5 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO1_5 |= 0x01; /* UART RTS */
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#if 1
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LPC_IOCON->DSR_LOC = 0;
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LPC_IOCON->PIO2_1 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO2_1 |= 0x01; /* UART DSR */
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LPC_IOCON->DCD_LOC = 0;
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LPC_IOCON->PIO2_2 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO2_2 |= 0x01; /* UART DCD */
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LPC_IOCON->RI_LOC = 0;
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LPC_IOCON->PIO2_3 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO2_3 |= 0x01; /* UART RI */
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#else
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LPC_IOCON->DSR_LOC = 1;
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LPC_IOCON->PIO3_1 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO3_1 |= 0x01; /* UART DSR */
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LPC_IOCON->DCD_LOC = 1;
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LPC_IOCON->PIO3_2 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO3_2 |= 0x01; /* UART DCD */
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LPC_IOCON->RI_LOC = 1;
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LPC_IOCON->PIO3_3 &= ~0x07; /* UART I/O config */
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LPC_IOCON->PIO3_3 |= 0x01; /* UART RI */
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#endif
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LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
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return;
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}
|
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#endif
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port, setup pin select,
|
||||
** clock, parity, stop bits, FIFO, etc.
|
||||
**
|
||||
** parameters: UART baudrate
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTInit(uint32_t baudrate)
|
||||
{
|
||||
uint32_t Fdiv;
|
||||
uint32_t regVal;
|
||||
|
||||
UARTTxEmpty = 1;
|
||||
UARTCount = 0;
|
||||
|
||||
NVIC_DisableIRQ(UART_IRQn);
|
||||
|
||||
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
|
||||
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
regVal = LPC_SYSCON->UARTCLKDIV;
|
||||
|
||||
Fdiv = (((SystemCoreClock*LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */
|
||||
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_USART->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
// CodeRed - added parentheses around comparison in operand of &
|
||||
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_USART->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(UART_IRQn);
|
||||
|
||||
#if CONFIG_UART_ENABLE_INTERRUPT==1
|
||||
#if CONFIG_UART_ENABLE_TX_INTERRUPT==1
|
||||
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
#else
|
||||
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
|
||||
#endif
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTSend
|
||||
**
|
||||
** Descriptions: Send a block of data to the UART 0 port based
|
||||
** on the data length
|
||||
**
|
||||
** parameters: buffer pointer, and data length
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
|
||||
{
|
||||
|
||||
while ( Length != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
#if CONFIG_UART_ENABLE_TX_INTERRUPT==1
|
||||
/* Below flag is set inside the interrupt handler when THRE occurs. */
|
||||
while ( !(UARTTxEmpty & 0x01) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
|
||||
#else
|
||||
while ( !(LPC_USART->LSR & LSR_THRE) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
#endif
|
||||
BufferPtr++;
|
||||
Length--;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
/*****************************************************************************
|
||||
* uart.c: UART API file for NXP LPC11xx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2008, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2009.12.07 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC11Uxx.h"
|
||||
#include "lpc11uxx_uart.h"
|
||||
|
||||
volatile uint32_t UARTStatus;
|
||||
volatile uint8_t UARTTxEmpty = 1;
|
||||
volatile uint8_t UARTBuffer[BUFSIZE];
|
||||
volatile uint32_t UARTCount = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UART_IRQHandler
|
||||
**
|
||||
** Descriptions: UART interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UART_IRQHandler(void)
|
||||
{
|
||||
uint8_t IIRValue, LSRValue;
|
||||
uint8_t Dummy = Dummy;
|
||||
|
||||
IIRValue = LPC_USART->IIR;
|
||||
|
||||
IIRValue >>= 1; /* skip pending bit in IIR */
|
||||
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
||||
if (IIRValue == IIR_RLS) /* Receive Line Status */
|
||||
{
|
||||
LSRValue = LPC_USART->LSR;
|
||||
/* Receive Line Status */
|
||||
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
|
||||
{
|
||||
/* There are errors or break interrupt */
|
||||
/* Read LSR will clear the interrupt */
|
||||
UARTStatus = LSRValue;
|
||||
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
|
||||
interrupt, then bail out */
|
||||
return;
|
||||
}
|
||||
if (LSRValue & LSR_RDR) /* Receive Data Ready */
|
||||
{
|
||||
/* If no error on RLS, normal ready, save into the data buffer. */
|
||||
/* Note: read RBR will clear the interrupt */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_RDA) /* Receive Data Available */
|
||||
{
|
||||
/* Receive Data Available */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
|
||||
{
|
||||
/* Character Time-out indicator */
|
||||
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
|
||||
}
|
||||
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
|
||||
{
|
||||
/* THRE interrupt */
|
||||
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
|
||||
valid data in U0THR or not */
|
||||
if (LSRValue & LSR_THRE)
|
||||
{
|
||||
UARTTxEmpty = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTTxEmpty = 0;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
#if MODEM_TEST
|
||||
/*****************************************************************************
|
||||
** Function name: ModemInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port as modem, setup pin select.
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void ModemInit( void )
|
||||
{
|
||||
LPC_IOCON->PIO2_0 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_0 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
|
||||
LPC_IOCON->PIO1_5 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_5 |= 0x01; /* UART RTS */
|
||||
#if 1
|
||||
LPC_IOCON->DSR_LOC = 0;
|
||||
LPC_IOCON->PIO2_1 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_1 |= 0x01; /* UART DSR */
|
||||
|
||||
LPC_IOCON->DCD_LOC = 0;
|
||||
LPC_IOCON->PIO2_2 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_2 |= 0x01; /* UART DCD */
|
||||
|
||||
LPC_IOCON->RI_LOC = 0;
|
||||
LPC_IOCON->PIO2_3 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO2_3 |= 0x01; /* UART RI */
|
||||
|
||||
#else
|
||||
LPC_IOCON->DSR_LOC = 1;
|
||||
LPC_IOCON->PIO3_1 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO3_1 |= 0x01; /* UART DSR */
|
||||
|
||||
LPC_IOCON->DCD_LOC = 1;
|
||||
LPC_IOCON->PIO3_2 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO3_2 |= 0x01; /* UART DCD */
|
||||
|
||||
LPC_IOCON->RI_LOC = 1;
|
||||
LPC_IOCON->PIO3_3 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO3_3 |= 0x01; /* UART RI */
|
||||
#endif
|
||||
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port, setup pin select,
|
||||
** clock, parity, stop bits, FIFO, etc.
|
||||
**
|
||||
** parameters: UART baudrate
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTInit(uint32_t baudrate)
|
||||
{
|
||||
uint32_t Fdiv;
|
||||
uint32_t regVal;
|
||||
|
||||
UARTTxEmpty = 1;
|
||||
UARTCount = 0;
|
||||
|
||||
NVIC_DisableIRQ(UART_IRQn);
|
||||
|
||||
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
|
||||
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
regVal = LPC_SYSCON->UARTCLKDIV;
|
||||
|
||||
Fdiv = (((SystemCoreClock*LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */
|
||||
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_USART->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
// CodeRed - added parentheses around comparison in operand of &
|
||||
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_USART->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(UART_IRQn);
|
||||
|
||||
#if CONFIG_UART_ENABLE_INTERRUPT==1
|
||||
#if CONFIG_UART_ENABLE_TX_INTERRUPT==1
|
||||
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
#else
|
||||
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
|
||||
#endif
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTSend
|
||||
**
|
||||
** Descriptions: Send a block of data to the UART 0 port based
|
||||
** on the data length
|
||||
**
|
||||
** parameters: buffer pointer, and data length
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
|
||||
{
|
||||
|
||||
while ( Length != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
#if CONFIG_UART_ENABLE_TX_INTERRUPT==1
|
||||
/* Below flag is set inside the interrupt handler when THRE occurs. */
|
||||
while ( !(UARTTxEmpty & 0x01) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
|
||||
#else
|
||||
while ( !(LPC_USART->LSR & LSR_THRE) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
#endif
|
||||
BufferPtr++;
|
||||
Length--;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
|
||||
@@ -1,55 +1,55 @@
|
||||
/*****************************************************************************
|
||||
* uart.h: Header file for NXP LPC1xxx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2008, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2009.12.07 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __UART_H
|
||||
#define __UART_H
|
||||
|
||||
#define RS485_ENABLED 0
|
||||
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
|
||||
#define MODEM_TEST 0
|
||||
|
||||
#define IER_RBR 0x01
|
||||
#define IER_THRE 0x02
|
||||
#define IER_RLS 0x04
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
|
||||
#define LSR_RDR 0x01
|
||||
#define LSR_OE 0x02
|
||||
#define LSR_PE 0x04
|
||||
#define LSR_FE 0x08
|
||||
#define LSR_BI 0x10
|
||||
#define LSR_THRE 0x20
|
||||
#define LSR_TEMT 0x40
|
||||
#define LSR_RXFE 0x80
|
||||
|
||||
#define BUFSIZE 0x40
|
||||
|
||||
/* RS485 mode definition. */
|
||||
#define RS485_NMMEN (0x1<<0)
|
||||
#define RS485_RXDIS (0x1<<1)
|
||||
#define RS485_AADEN (0x1<<2)
|
||||
#define RS485_SEL (0x1<<3)
|
||||
#define RS485_DCTRL (0x1<<4)
|
||||
#define RS485_OINV (0x1<<5)
|
||||
|
||||
void ModemInit( void );
|
||||
void UARTInit(uint32_t Baudrate);
|
||||
void UART_IRQHandler(void);
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
|
||||
|
||||
#endif /* end __UART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
/*****************************************************************************
|
||||
* uart.h: Header file for NXP LPC1xxx Family Microprocessors
|
||||
*
|
||||
* Copyright(C) 2008, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2009.12.07 ver 1.00 Preliminary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __UART_H
|
||||
#define __UART_H
|
||||
|
||||
#define RS485_ENABLED 0
|
||||
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
|
||||
#define MODEM_TEST 0
|
||||
|
||||
#define IER_RBR 0x01
|
||||
#define IER_THRE 0x02
|
||||
#define IER_RLS 0x04
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
|
||||
#define LSR_RDR 0x01
|
||||
#define LSR_OE 0x02
|
||||
#define LSR_PE 0x04
|
||||
#define LSR_FE 0x08
|
||||
#define LSR_BI 0x10
|
||||
#define LSR_THRE 0x20
|
||||
#define LSR_TEMT 0x40
|
||||
#define LSR_RXFE 0x80
|
||||
|
||||
#define BUFSIZE 0x40
|
||||
|
||||
/* RS485 mode definition. */
|
||||
#define RS485_NMMEN (0x1<<0)
|
||||
#define RS485_RXDIS (0x1<<1)
|
||||
#define RS485_AADEN (0x1<<2)
|
||||
#define RS485_SEL (0x1<<3)
|
||||
#define RS485_DCTRL (0x1<<4)
|
||||
#define RS485_OINV (0x1<<5)
|
||||
|
||||
void ModemInit( void );
|
||||
void UARTInit(uint32_t Baudrate);
|
||||
void UART_IRQHandler(void);
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
|
||||
|
||||
#endif /* end __UART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
|
||||
Reference in New Issue
Block a user