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Merge branch 'hathach:master' into master

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沈玴興
2023-12-28 00:29:41 +08:00
committed by GitHub
parent 9a1559a356 ae364b1460
commit 149b50a2fa
74 changed files with 2067 additions and 734 deletions
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5
src/common/tusb_mcu.h
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@@ -210,6 +210,11 @@
#define TUP_DCD_ENDPOINT_MAX 9
#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
#define TUP_USBIP_FSDEV
#define TUP_USBIP_FSDEV_STM32
#define TUP_DCD_ENDPOINT_MAX 8
#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
// Device controller
#define TUP_USBIP_FSDEV

36
src/portable/analog/max3421/hcd_max3421.c
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@@ -171,6 +171,8 @@ enum {
//--------------------------------------------------------------------+
typedef struct {
uint8_t daddr;
struct TU_ATTR_PACKED {
uint8_t ep_dir : 1;
uint8_t is_iso : 1;
@@ -179,17 +181,19 @@ typedef struct {
uint8_t xfer_pending : 1;
uint8_t xfer_complete : 1;
};
struct TU_ATTR_PACKED {
uint8_t daddr : 4;
uint8_t ep_num : 4;
uint16_t packet_size : 12;
};
uint16_t packet_size;
uint16_t total_len;
uint16_t xferred_len;
uint8_t* buf;
} max3421_ep_t;
TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct");
typedef struct {
// cached register
uint8_t sndbc;
@@ -320,7 +324,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
reg_write(rhport, HIRQ_ADDR, data, in_isr);
// HIRQ write 1 is clear
_hcd_data.hirq &= ~data;
_hcd_data.hirq &= (uint8_t) ~data;
}
static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
@@ -390,7 +394,7 @@ static void free_ep(uint8_t daddr) {
}
static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
size_t const idx = cur_ep - _hcd_data.ep;
size_t const idx = (size_t) (cur_ep - _hcd_data.ep);
// starting from next endpoint
for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
@@ -537,8 +541,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
(void) rhport;
(void) daddr;
uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
uint8_t const ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
tusb_dir_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
max3421_ep_t * ep;
if (daddr == 0 && ep_num == 0) {
@@ -547,15 +551,15 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
ep = allocate_ep();
TU_ASSERT(ep);
ep->daddr = daddr;
ep->ep_num = ep_num;
ep->ep_dir = ep_dir;
ep->ep_num = (uint8_t) (ep_num & 0x0f);
ep->ep_dir = (ep_dir == TUSB_DIR_IN) ? 1 : 0;
}
if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
ep->is_iso = 1;
}
ep->packet_size = tu_edpt_packet_size(ep_desc);
ep->packet_size = (uint16_t) (tu_edpt_packet_size(ep_desc) & 0x7ff);
return true;
}
@@ -577,7 +581,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
}
sndbc_write(rhport, xact_len, in_isr);
uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
uint8_t const hxfr = (uint8_t ) (ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0));
hxfr_write(rhport, hxfr, in_isr);
}
@@ -590,7 +594,7 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
reg_write(rhport, HCTL_ADDR, hctl, in_isr);
}
uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
uint8_t const hxfr = (uint8_t) (ep->ep_num | (ep->is_iso ? HXFR_ISO : 0));
hxfr_write(rhport, hxfr, in_isr);
}
@@ -623,13 +627,13 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
uint8_t const ep_num = tu_edpt_number(ep_addr);
uint8_t const ep_dir = tu_edpt_dir(ep_addr);
uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
TU_VERIFY(ep);
// control transfer can switch direction
ep->ep_dir = ep_dir;
ep->ep_dir = ep_dir ? 1u : 0u;
ep->buf = buffer;
ep->total_len = buflen;
@@ -748,9 +752,9 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
// save data toggle
if (ep->ep_dir) {
ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1u : 0u;
}else {
ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1u : 0u;
}
ep->xfer_pending = 0;
@@ -929,7 +933,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
}
// clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
hirq &= ~HIRQ_SNDBAV_IRQ;
hirq &= (uint8_t) ~HIRQ_SNDBAV_IRQ;
if ( hirq ) {
hirq_write(rhport, hirq, in_isr);
}

7
src/portable/nordic/nrf5x/dcd_nrf5x.c
View File

@@ -340,6 +340,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
NRF_USBD->EPINEN |= TU_BIT(epnum);
}
// clear stall and reset DataToggle
NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
}
else
{
@@ -375,10 +378,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
}
}
// clear stall and reset DataToggle
NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
__ISB(); __DSB();
return true;

2
src/portable/raspberrypi/rp2040/hcd_rp2040.c
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@@ -27,7 +27,7 @@
#include "tusb_option.h"
#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB
#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB && !CFG_TUH_MAX3421
#include "pico.h"
#include "rp2040_usb.h"

8
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
View File

@@ -242,7 +242,7 @@ void dcd_init (uint8_t rhport)
}
USB->CNTR = 0; // Enable USB
#ifndef STM32G0 // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
#if !defined(STM32G0) && !defined(STM32H5) // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
USB->BTABLE = DCD_STM32_BTABLE_BASE;
#endif
USB->ISTR = 0; // Clear pending interrupts
@@ -358,6 +358,9 @@ void dcd_int_enable (uint8_t rhport)
NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
#endif
#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
NVIC_EnableIRQ(USB_DRD_FS_IRQn);
#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
NVIC_EnableIRQ(USB_HP_IRQn);
NVIC_EnableIRQ(USB_LP_IRQn);
@@ -415,6 +418,9 @@ void dcd_int_disable(uint8_t rhport)
NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
#endif
#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
NVIC_DisableIRQ(USB_DRD_FS_IRQn);
#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
NVIC_DisableIRQ(USB_HP_IRQn);
NVIC_DisableIRQ(USB_LP_IRQn);

29
src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
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@@ -110,6 +110,35 @@
#define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
#define USB_CNTR_FSUSP USB_CNTR_SUSPEN
#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
#include "stm32h5xx.h"
#define PMA_32BIT_ACCESS
#define PMA_LENGTH (2048u)
#undef USB_PMAADDR
#define USB_PMAADDR USB_DRD_PMAADDR
#define USB_TypeDef USB_DRD_TypeDef
#define EP0R CHEP0R
#define USB_EP_CTR_RX USB_EP_VTRX
#define USB_EP_CTR_TX USB_EP_VTTX
#define USB_EP_T_FIELD USB_CHEP_UTYPE
#define USB_EPREG_MASK USB_CHEP_REG_MASK
#define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
#define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
#define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
#define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
#define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
#define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
#define USB_EPRX_STAT USB_CH_RX_VALID
#define USB_EPKIND_MASK USB_EP_KIND_MASK
#define USB USB_DRD_FS
#define USB_CNTR_FRES USB_CNTR_USBRST
#define USB_CNTR_RESUME USB_CNTR_L2RES
#define USB_ISTR_EP_ID USB_ISTR_IDN
#define USB_EPADDR_FIELD USB_CHEP_ADDR
#define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
#define USB_CNTR_FSUSP USB_CNTR_SUSPEN
#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
#include "stm32wbxx.h"
#define PMA_LENGTH (1024u)

1
src/tusb_option.h
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@@ -86,6 +86,7 @@
#define OPT_MCU_STM32WB 312 ///< ST WB
#define OPT_MCU_STM32U5 313 ///< ST U5
#define OPT_MCU_STM32L5 314 ///< ST L5
#define OPT_MCU_STM32H5 315 ///< ST H5
// Sony
#define OPT_MCU_CXD56 400 ///< SONY CXD56