simplify tusb_dcd_edpt_xfer API
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@@ -126,7 +126,7 @@ tusb_error_t mscd_open(uint8_t port, tusb_descriptor_interface_t const * p_inter
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(*p_length) += sizeof(tusb_descriptor_interface_t) + 2*sizeof(tusb_descriptor_endpoint_t);
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//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t), true), TUSB_ERROR_DCD_EDPT_XFER );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_DCD_EDPT_XFER );
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return TUSB_ERROR_NONE;
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}
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@@ -251,10 +251,10 @@ tusb_error_t mscd_xfer_cb(uint8_t port, uint8_t ep_addr, tusb_event_t event, uin
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// Move to default CMD stage after sending status
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p_msc->stage = MSC_STAGE_CMD;
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t), true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
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//------------- Queue the next CBW -------------//
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t), true) );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
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}
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return TUSB_ERROR_NONE;
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@@ -300,7 +300,7 @@ static bool read10_write10_data_xfer(uint8_t port, mscd_interface_t* p_msc)
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return true;
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} else if (xfer_block < block_count)
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{
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TU_ASSERT( tusb_dcd_edpt_xfer(port, ep_addr, p_buffer, xfer_byte, true), TUSB_ERROR_DCD_EDPT_XFER );
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TU_ASSERT( tusb_dcd_edpt_xfer(port, ep_addr, p_buffer, xfer_byte), TUSB_ERROR_DCD_EDPT_XFER );
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// adjust lba, block_count, xfer_bytes for the next call
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p_readwrite->lba = __n2be(lba+xfer_block);
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