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add hal init for USB1 and trying to get USB1 working

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add hack delay 100 ms after a port reset (huge) for correct speed detection
This commit is contained in:
hathach
2013-04-07 03:40:24 +07:00
parent b5f7e48ad4
commit 1776bb53f6
9 changed files with 166 additions and 27 deletions
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33
tinyusb/hal/hal_lpc43xx.c
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@@ -55,19 +55,42 @@ enum {
tusb_error_t hal_init(void)
{
/* Set up USB0 clock */
//------------- USB0 Clock -------------//
#if TUSB_CFG_CONTROLLER0_MODE
CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
ASSERT_INT( CGU_ERROR_SUCCESS, CGU_SetPLL0(), TUSB_ERROR_FAILED); /* the usb core require output clock = 480MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE); /* Enable PLL after all setting is done */
LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
//------------- reset controller & set role -------------//
hcd_controller_reset(0); // TODO where to place prototype, USB1
// reset controller & set role
#if TUSB_CFG_CONTROLLER0_MODE & TUSB_MODE_HOST
hcd_controller_reset(0); // TODO where to place prototype
LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else // TODO OTG
#error device mode is not supported
#endif
hal_interrupt_enable(0); // TODO USB1
hal_interrupt_enable(0);
#endif
//------------- USB1 Clock, only use on-chip FS PHY -------------//
#if TUSB_CFG_CONTROLLER1_MODE
/* connect CLK_USB1 to 60 MHz clock */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); /* FIXME Run base BASE_USB1_CLK clock from PLL1 (assume PLL1 is 60 MHz, no division required) */
LPC_SCU->SFSUSB = (TUSB_CFG_CONTROLLER1_MODE & TUSB_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
#if TUSB_CFG_CONTROLLER1_MODE & TUSB_MODE_HOST
hcd_controller_reset(1); // TODO where to place prototype
LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
#else
#endif
LPC_USB1->PORTSC1_D |= (1<<24); // TODO abtract, force port to fullspeed
hal_interrupt_enable(1);
#endif
return TUSB_ERROR_NONE;
}

6
tinyusb/host/ehci/ehci.c
View File

@@ -136,6 +136,10 @@ void hcd_port_reset(uint8_t hostid)
// there is chance device is unplugged while reset sequence is not complete
while( regs->portsc_bit.port_reset) {}
#endif
// TODO finalize delay after reset, hack delay 100 ms, otherwise speed is detected as LOW in most cases
volatile uint32_t delay_us = 100000;
delay_us *= (SystemCoreClock / 1000000) / 3;
while(delay_us--);
}
bool hcd_port_connect_status(uint8_t hostid)
@@ -153,7 +157,9 @@ static tusb_error_t hcd_controller_init(uint8_t hostid)
//------------- CTRLDSSEGMENT Register (skip) -------------//
//------------- USB INT Register -------------//
regs->usb_int_enable = 0; // 1. disable all the interrupt
#ifndef _TEST_ // the fake controller does not have write-to-clear behavior
regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status
#endif
regs->usb_int_enable = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
#if EHCI_PERIODIC_LIST
EHCI_INT_MASK_NXP_PERIODIC |

15
tinyusb/osal/osal.h
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@@ -141,8 +141,8 @@ tusb_error_t osal_task_create(osal_task_t *task);
//--------------------------------------------------------------------+
// Semaphore API
//--------------------------------------------------------------------+
typedef volatile uint32_t osal_semaphore_t;
typedef void* osal_semaphore_handle_t;
typedef volatile uint8_t osal_semaphore_t;
typedef osal_semaphore_t * osal_semaphore_handle_t;
#define OSAL_SEM_DEF(name)\
osal_semaphore_t name
@@ -158,8 +158,15 @@ void osal_semaphore_reset(osal_semaphore_handle_t const sem_hdl);
//--------------------------------------------------------------------+
// QUEUE API
//--------------------------------------------------------------------+
typedef uint32_t osal_queue_t;
typedef void* osal_queue_handle_t;
typedef struct{
uint32_t * const buffer ; ///< buffer pointer
uint8_t const depth ; ///< buffer size
volatile uint8_t count ; ///< bytes in fifo
volatile uint8_t wr_idx ; ///< write pointer
volatile uint8_t rd_idx ; ///< read pointer
} osal_queue_t;
typedef osal_queue_t * osal_queue_handle_t;
#define OSAL_QUEUE_DEF(name, queue_depth, type) \
osal_queue_t name

4
tinyusb/osal/osal_none.h
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@@ -67,8 +67,8 @@ static inline void osal_tick_tock(void)
osal_tick_current++;
}
static inline uint32_t osal_tick_get(void) ATTR_ALWAYS_INLINE;
static inline uint32_t osal_tick_get(void)
static inline volatile uint32_t osal_tick_get(void) ATTR_ALWAYS_INLINE;
static inline volatile uint32_t osal_tick_get(void)
{
return osal_tick_current;
}