Bunny brain board created, but not modified yet
Bunny brain board created, but not modified yet
This commit is contained in:
Jerry Palacios
338
hw/bsp/mcx/boards/bunny-brain/clock_config.c
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338
hw/bsp/mcx/boards/bunny-brain/clock_config.c
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/*
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* Copyright 2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Set up wait states of the flash.
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*
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* 3. Set up all dividers.
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*
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* 4. Set up all selectors to provide selected clocks.
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*
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v10.0
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processor: MCXN947
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package_id: MCXN947VDF
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mcu_data: ksdk2_0
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processor_version: 0.12.3
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board: MCX-N9XX-EVK
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "clock_config.h"
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#include "fsl_clock.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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// extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockPLL150M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO12M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO12M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: MAIN_clock.outFreq, value: 12 MHz}
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- {id: Slow_clock.outFreq, value: 3 MHz}
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- {id: System_clock.outFreq, value: 12 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SCGMode, value: SIRC}
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- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
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- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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void BOARD_BootClockFRO12M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF48M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF48M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 48 MHz}
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- {id: Slow_clock.outFreq, value: 12 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF48M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF144M ********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF144M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_clock.outFreq, value: 144 MHz}
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- {id: MAIN_clock.outFreq, value: 144 MHz}
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- {id: Slow_clock.outFreq, value: 18 MHz}
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- {id: System_clock.outFreq, value: 72 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
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- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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sources:
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- {id: SCG.FIRC.outFreq, value: 144 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF144M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF144M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF144M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U); /*!< Set AHBCLKDIV divider to value 2 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL150M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL150M
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called_from_default_init: true
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 150 MHz}
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- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
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- {id: Slow_clock.outFreq, value: 37.5 MHz}
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- {id: System_clock.outFreq, value: 150 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: PLL0_Mode, value: Normal}
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- {id: RunPowerMode, value: OD}
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- {id: SCGMode, value: PLL0}
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- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
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- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
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- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
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- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
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- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL150M configuration
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******************************************************************************/
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void BOARD_BootClockPLL150M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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/*!< Set up PLL0 */
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const pll_setup_t pll0Setup = {
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.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
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.pllndiv = SCG_APLLNDIV_NDIV(8U),
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.pllpdiv = SCG_APLLPDIV_PDIV(1U),
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.pllmdiv = SCG_APLLMDIV_MDIV(50U),
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.pllRate = 150000000U
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};
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CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
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CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockPLL100M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockPLL100M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: CLK_IN_clock.outFreq, value: 24 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: MAIN_clock.outFreq, value: 100 MHz}
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- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
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- {id: Slow_clock.outFreq, value: 25 MHz}
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- {id: System_clock.outFreq, value: 100 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: PLL1_Mode, value: Normal}
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- {id: SCGMode, value: PLL1}
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- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
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- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
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- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
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- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
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- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
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- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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sources:
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- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockPLL100M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockPLL100M configuration
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******************************************************************************/
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void BOARD_BootClockPLL100M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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CLOCK_SetupExtClocking(24000000U);
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CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
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/*!< Set up PLL1 */
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const pll_setup_t pll1Setup = {
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.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
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.pllndiv = SCG_SPLLNDIV_NDIV(6U),
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.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
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.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
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.pllRate = 100000000U
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};
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CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
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CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
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}
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Reference in New Issue
Block a user