change dcd 176x alignment placement to work with IAR
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@@ -55,7 +55,7 @@
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#define DCD_QTD_MAX 32 // TODO scale with configure
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typedef struct {
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volatile ATTR_ALIGNED(128) dcd_dma_descriptor_t* udca[DCD_QHD_MAX];
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volatile dcd_dma_descriptor_t* udca[DCD_QHD_MAX]; // must be 128 byte aligned
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dcd_dma_descriptor_t dd[DCD_QTD_MAX][2]; // each endpoints can have up to 2 DD queued at a time TODO 0-1 are not used, offset to reduce memory
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uint8_t class_code[DCD_QHD_MAX];
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@@ -68,7 +68,7 @@ typedef struct {
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}dcd_data_t;
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TUSB_CFG_ATTR_USBRAM STATIC_ dcd_data_t dcd_data;
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TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(128) STATIC_ dcd_data_t dcd_data;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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