usbd: fix control transfer issue for chipidea hs when previous status and new setup complete in the same isr frame
change usbd edpt busy/stalled/claimed value to 0/1 instead of (true/false) since they are 1-bit field.
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@@ -616,15 +616,6 @@ void dcd_int_handler(uint8_t rhport)
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uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
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dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
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if (dcd_reg->ENDPTSETUPSTAT)
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{
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//------------- Set up Received -------------//
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// 23.10.10.2 Operational model for setup transfers
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dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
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dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
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}
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// 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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// nothing to do, we will submit xfer as error to usbd
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// if (int_status & INTR_ERROR) { }
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@@ -637,6 +628,15 @@ void dcd_int_handler(uint8_t rhport)
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if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
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}
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}
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// Set up Received
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// 23.10.10.2 Operational model for setup transfers
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// Must be after normal transfer complete since it is possible to have both previous control status + new setup
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// in the same frame and we should handle previous status first.
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if (dcd_reg->ENDPTSETUPSTAT) {
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dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
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dcd_event_setup_received(rhport, (uint8_t *) (uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
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}
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}
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if (int_status & INTR_SOF)
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