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Enhance chipidea (#2075)

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* update chipidea dcd, remove manual ep_count and use DCCPARAMS to get number of endpoint instead
* add dcd dcache for chipidea
* add cmake for lpc18
* add makefile build for mcx
* use fork of mcu sdk
* fix ci build with nrf
* flash rp2040 with openocd
This commit is contained in:
Ha Thach
2023-05-23 21:45:00 +07:00
committed by GitHub
parent c998e9c60b
commit 1ef820ecfe
42 changed files with 1915 additions and 122 deletions
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21
src/portable/chipidea/ci_hs/hcd_ci_hs.c
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@@ -42,28 +42,17 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
#include "ci_hs_imxrt.h"
// check if memory is cacheable i.e not in DTCM
TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) {
return !(0x20000000 <= addr && addr < 0x20100000);
}
void hcd_dcache_clean(void* addr, uint32_t data_size) {
if (is_cache_mem((uint32_t) addr)) {
SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
}
imxrt_dcache_clean(addr, data_size);
}
void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
if (is_cache_mem((uint32_t) addr)) {
SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
}
imxrt_dcache_invalidate(addr, data_size);
}
void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
if (is_cache_mem((uint32_t) addr)) {
SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
imxrt_dcache_clean_invalidate(addr, data_size);
}
}
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h"
@@ -75,8 +64,6 @@ void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+