change the tusb_rhport_init_t struct, exclude the rhport to make API more consistent
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@@ -267,9 +267,9 @@ static void process_bus_resume(uint8_t rhport)
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/*------------------------------------------------------------------*/
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/* Device API
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*------------------------------------------------------------------*/
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void dcd_init(const tusb_rhport_init_t* rh_init) {
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const uint8_t rhport = rh_init->rhport;
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void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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(void) rhport;
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(void) rh_init;
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// save crystal-less setting (if available)
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#if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
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@@ -234,8 +234,8 @@ static void bus_reset(uint8_t rhport)
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dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
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}
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void dcd_init(const tusb_rhport_init_t* rh_init) {
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const uint8_t rhport = rh_init->rhport;
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void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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(void) rh_init;
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
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@@ -70,8 +70,8 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
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// Controller API
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//--------------------------------------------------------------------+
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bool hcd_init(const tusb_rhport_init_t* rh_init) {
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const uint8_t rhport = rh_init->rhport;
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bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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(void) rh_init;
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ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport);
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// Reset controller
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@@ -83,7 +83,9 @@ bool hcd_init(const tusb_rhport_init_t* rh_init) {
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// LPC18XX/43XX need to set VBUS Power Select to HIGH
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// RHPORT1 is fullspeed only (need external PHY for Highspeed)
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hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
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if ( rhport == 1 ) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
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if (rhport == 1) {
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hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
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}
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#else
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hcd_reg->USBMODE = USBMODE_CM_HOST;
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#endif
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