Implement requested PR changes
Removes CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT, and makes the manual padding behavior standard. Replaced unused variable name with TU_RESERVED.
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@@ -231,11 +231,6 @@ typedef struct TU_ATTR_ALIGNED(32)
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uint32_t : 1; ///< reserved
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uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator.
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uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT.
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#if CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT
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///< All 32 bits are used
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#else
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uint32_t : 0; // padding to the end of current storage unit
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#endif /* CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT */
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// Word 2: Micro-frame Schedule Control
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uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
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@@ -427,11 +422,7 @@ typedef volatile struct
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uint32_t nxp_port_force_fullspeed : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
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uint32_t : 1;
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uint32_t nxp_port_speed : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
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#if CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT
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uint32_t unused : 4; ///< padding
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#else
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uint32_t : 0; // padding to the boundary of storage unit
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#endif /* CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT */
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uint32_t TU_RESERVED : 4;
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}portsc_bm;
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};
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}ehci_registers_t;
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@@ -163,11 +163,7 @@ typedef struct {
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uint16_t high_speed : 1;
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uint16_t port_test_mode : 1;
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uint16_t port_indicator_control : 1;
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#if CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT
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uint16_t unused : 3;
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#else
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uint16_t : 0;
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#endif /* CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT */
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uint16_t TU_RESERVED : 3;
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};
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uint16_t value;
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@@ -208,11 +208,7 @@ typedef volatile struct
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uint32_t interrupt_routing : 1;
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uint32_t remote_wakeup_connected : 1;
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uint32_t remote_wakeup_enale : 1;
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#if CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT
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uint32_t unused : 21;
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#else
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uint32_t : 0;
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#endif /* CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT */
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uint32_t TU_RESERVED : 21;
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}control_bit;
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};
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@@ -280,11 +276,7 @@ typedef volatile struct
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uint32_t port_suspend_status_change : 1;
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uint32_t port_over_current_indicator_change : 1;
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uint32_t port_reset_status_change : 1;
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#if CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT
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uint32_t unused : 11;
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#else
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uint32_t : 0;
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#endif /* CFG_TUSB_ALT_BIT_PACKING_ALIGNMENT */
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uint32_t TU_RESERVED : 11;
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}rhport_status_bit[2];
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};
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}ohci_registers_t;
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