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@@ -43,16 +43,14 @@
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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enum
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enum {
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{
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MSC_STAGE_IDLE = 0,
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MSC_STAGE_IDLE = 0,
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MSC_STAGE_CMD,
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MSC_STAGE_CMD,
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MSC_STAGE_DATA,
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MSC_STAGE_DATA,
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MSC_STAGE_STATUS,
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MSC_STAGE_STATUS,
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};
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};
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typedef struct
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typedef struct {
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{
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uint8_t itf_num;
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uint8_t itf_num;
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uint8_t ep_in;
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uint8_t ep_in;
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uint8_t ep_out;
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uint8_t ep_out;
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@@ -75,7 +73,7 @@ typedef struct
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CFG_TUH_MEM_ALIGN msc_cbw_t cbw;
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CFG_TUH_MEM_ALIGN msc_cbw_t cbw;
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CFG_TUH_MEM_ALIGN msc_csw_t csw;
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CFG_TUH_MEM_ALIGN msc_csw_t csw;
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}msch_interface_t;
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} msch_interface_t;
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CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
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CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
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@@ -86,40 +84,34 @@ static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
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// FIXME potential nul reference
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// FIXME potential nul reference
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TU_ATTR_ALWAYS_INLINE
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TU_ATTR_ALWAYS_INLINE
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static inline msch_interface_t* get_itf(uint8_t dev_addr)
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static inline msch_interface_t* get_itf(uint8_t dev_addr) {
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{
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return &_msch_itf[dev_addr - 1];
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return &_msch_itf[dev_addr-1];
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}
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}
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// PUBLIC API
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// PUBLIC API
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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uint8_t tuh_msc_get_maxlun(uint8_t dev_addr)
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uint8_t tuh_msc_get_maxlun(uint8_t dev_addr) {
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{
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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return p_msc->max_lun;
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return p_msc->max_lun;
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}
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}
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uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun)
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uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun) {
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{
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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return p_msc->capacity[lun].block_count;
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return p_msc->capacity[lun].block_count;
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}
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}
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uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun)
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uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun) {
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{
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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return p_msc->capacity[lun].block_size;
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return p_msc->capacity[lun].block_size;
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}
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}
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bool tuh_msc_mounted(uint8_t dev_addr)
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bool tuh_msc_mounted(uint8_t dev_addr) {
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{
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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return p_msc->mounted;
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return p_msc->mounted;
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}
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}
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bool tuh_msc_ready(uint8_t dev_addr)
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bool tuh_msc_ready(uint8_t dev_addr) {
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{
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out);
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return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out);
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}
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}
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@@ -127,20 +119,20 @@ bool tuh_msc_ready(uint8_t dev_addr)
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// PUBLIC API: SCSI COMMAND
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// PUBLIC API: SCSI COMMAND
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun)
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static inline void cbw_init(msc_cbw_t* cbw, uint8_t lun) {
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{
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tu_memclr(cbw, sizeof(msc_cbw_t));
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tu_memclr(cbw, sizeof(msc_cbw_t));
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cbw->signature = MSC_CBW_SIGNATURE;
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cbw->signature = MSC_CBW_SIGNATURE;
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cbw->tag = 0x54555342; // TUSB
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cbw->tag = 0x54555342; // TUSB
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cbw->lun = lun;
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cbw->lun = lun;
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}
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}
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bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
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bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data,
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{
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tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(daddr);
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TU_VERIFY(p_msc->configured);
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TU_VERIFY(p_msc->configured);
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// TODO claim endpoint
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// claim endpoint
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TU_VERIFY(usbh_edpt_claim(daddr, p_msc->ep_out));
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p_msc->cbw = *cbw;
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p_msc->cbw = *cbw;
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p_msc->stage = MSC_STAGE_CMD;
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p_msc->stage = MSC_STAGE_CMD;
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@@ -148,13 +140,16 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu
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p_msc->complete_cb = complete_cb;
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p_msc->complete_cb = complete_cb;
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p_msc->complete_arg = arg;
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p_msc->complete_arg = arg;
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TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)));
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if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))) {
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usbh_edpt_release(daddr, p_msc->ep_out);
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return false;
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}
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return true;
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return true;
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}
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}
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bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
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bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response,
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{
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tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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TU_VERIFY(p_msc->configured);
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TU_VERIFY(p_msc->configured);
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@@ -169,8 +164,8 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r
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return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
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return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
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}
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}
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bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
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bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response,
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{
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tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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TU_VERIFY(p_msc->mounted);
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TU_VERIFY(p_msc->mounted);
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@@ -181,8 +176,7 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
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cbw.dir = TUSB_DIR_IN_MASK;
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cbw.dir = TUSB_DIR_IN_MASK;
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cbw.cmd_len = sizeof(scsi_inquiry_t);
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cbw.cmd_len = sizeof(scsi_inquiry_t);
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scsi_inquiry_t const cmd_inquiry =
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scsi_inquiry_t const cmd_inquiry = {
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{
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.cmd_code = SCSI_CMD_INQUIRY,
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.cmd_code = SCSI_CMD_INQUIRY,
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.alloc_length = sizeof(scsi_inquiry_resp_t)
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.alloc_length = sizeof(scsi_inquiry_resp_t)
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};
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};
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@@ -191,8 +185,7 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
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return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
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return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
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}
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}
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bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
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bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
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{
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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TU_VERIFY(p_msc->configured);
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TU_VERIFY(p_msc->configured);
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@@ -208,8 +201,8 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
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return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
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return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
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}
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}
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bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
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bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void* response,
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{
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tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
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msc_cbw_t cbw;
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msc_cbw_t cbw;
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cbw_init(&cbw, lun);
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cbw_init(&cbw, lun);
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@@ -217,73 +210,64 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_ms
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cbw.dir = TUSB_DIR_IN_MASK;
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cbw.dir = TUSB_DIR_IN_MASK;
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cbw.cmd_len = sizeof(scsi_request_sense_t);
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cbw.cmd_len = sizeof(scsi_request_sense_t);
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scsi_request_sense_t const cmd_request_sense =
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scsi_request_sense_t const cmd_request_sense = {
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{
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.cmd_code = SCSI_CMD_REQUEST_SENSE,
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.cmd_code = SCSI_CMD_REQUEST_SENSE,
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.alloc_length = 18
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.alloc_length = 18
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};
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};
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memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
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memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
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return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
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return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
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}
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}
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bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
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bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void* buffer, uint32_t lba, uint16_t block_count,
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{
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tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
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msch_interface_t* p_msc = get_itf(dev_addr);
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msch_interface_t* p_msc = get_itf(dev_addr);
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TU_VERIFY(p_msc->mounted);
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TU_VERIFY(p_msc->mounted);
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msc_cbw_t cbw;
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msc_cbw_t cbw;
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cbw_init(&cbw, lun);
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cbw_init(&cbw, lun);
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cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
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cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
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cbw.dir = TUSB_DIR_IN_MASK;
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cbw.dir = TUSB_DIR_IN_MASK;
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cbw.cmd_len = sizeof(scsi_read10_t);
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cbw.cmd_len = sizeof(scsi_read10_t);
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scsi_read10_t const cmd_read10 =
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scsi_read10_t const cmd_read10 = {
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{
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.cmd_code = SCSI_CMD_READ_10,
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.cmd_code = SCSI_CMD_READ_10,
|
|
|
|
.lba = tu_htonl(lba),
|
|
|
|
.lba = tu_htonl(lba),
|
|
|
|
.block_count = tu_htons(block_count)
|
|
|
|
.block_count = tu_htons(block_count)
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
|
|
|
|
memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
|
|
|
|
|
|
|
|
|
|
|
|
return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
|
|
|
|
return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
|
|
|
|
bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const* buffer, uint32_t lba, uint16_t block_count,
|
|
|
|
{
|
|
|
|
tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
TU_VERIFY(p_msc->mounted);
|
|
|
|
TU_VERIFY(p_msc->mounted);
|
|
|
|
|
|
|
|
|
|
|
|
msc_cbw_t cbw;
|
|
|
|
msc_cbw_t cbw;
|
|
|
|
cbw_init(&cbw, lun);
|
|
|
|
cbw_init(&cbw, lun);
|
|
|
|
|
|
|
|
|
|
|
|
cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
|
|
|
|
cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
|
|
|
|
cbw.dir = TUSB_DIR_OUT;
|
|
|
|
cbw.dir = TUSB_DIR_OUT;
|
|
|
|
cbw.cmd_len = sizeof(scsi_write10_t);
|
|
|
|
cbw.cmd_len = sizeof(scsi_write10_t);
|
|
|
|
|
|
|
|
|
|
|
|
scsi_write10_t const cmd_write10 =
|
|
|
|
scsi_write10_t const cmd_write10 = {
|
|
|
|
{
|
|
|
|
|
|
|
|
.cmd_code = SCSI_CMD_WRITE_10,
|
|
|
|
.cmd_code = SCSI_CMD_WRITE_10,
|
|
|
|
.lba = tu_htonl(lba),
|
|
|
|
.lba = tu_htonl(lba),
|
|
|
|
.block_count = tu_htons(block_count)
|
|
|
|
.block_count = tu_htons(block_count)
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
|
|
|
|
memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
|
|
|
|
|
|
|
|
|
|
|
|
return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb, arg);
|
|
|
|
return tuh_msc_scsi_command(dev_addr, &cbw, (void*) (uintptr_t) buffer, complete_cb, arg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
#if 0
|
|
|
|
// MSC interface Reset (not used now)
|
|
|
|
// MSC interface Reset (not used now)
|
|
|
|
bool tuh_msc_reset(uint8_t dev_addr)
|
|
|
|
bool tuh_msc_reset(uint8_t dev_addr) {
|
|
|
|
{
|
|
|
|
tusb_control_request_t const new_request = {
|
|
|
|
tusb_control_request_t const new_request =
|
|
|
|
.bmRequestType_bit = {
|
|
|
|
{
|
|
|
|
|
|
|
|
.bmRequestType_bit =
|
|
|
|
|
|
|
|
{
|
|
|
|
|
|
|
|
.recipient = TUSB_REQ_RCPT_INTERFACE,
|
|
|
|
.recipient = TUSB_REQ_RCPT_INTERFACE,
|
|
|
|
.type = TUSB_REQ_TYPE_CLASS,
|
|
|
|
.type = TUSB_REQ_TYPE_CLASS,
|
|
|
|
.direction = TUSB_DIR_OUT
|
|
|
|
.direction = TUSB_DIR_OUT
|
|
|
@@ -300,48 +284,41 @@ bool tuh_msc_reset(uint8_t dev_addr)
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
// CLASS-USBH API
|
|
|
|
// CLASS-USBH API
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
void msch_init(void)
|
|
|
|
void msch_init(void) {
|
|
|
|
{
|
|
|
|
|
|
|
|
tu_memclr(_msch_itf, sizeof(_msch_itf));
|
|
|
|
tu_memclr(_msch_itf, sizeof(_msch_itf));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void msch_close(uint8_t dev_addr)
|
|
|
|
void msch_close(uint8_t dev_addr) {
|
|
|
|
{
|
|
|
|
TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,);
|
|
|
|
TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
|
|
|
|
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
TU_VERIFY(p_msc->configured, );
|
|
|
|
TU_VERIFY(p_msc->configured,);
|
|
|
|
|
|
|
|
|
|
|
|
TU_LOG_DRV(" MSCh close addr = %d\r\n", dev_addr);
|
|
|
|
TU_LOG_DRV(" MSCh close addr = %d\r\n", dev_addr);
|
|
|
|
|
|
|
|
|
|
|
|
// invoke Application Callback
|
|
|
|
// invoke Application Callback
|
|
|
|
if (p_msc->mounted) {
|
|
|
|
if (p_msc->mounted) {
|
|
|
|
if(tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
|
|
|
|
if (tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
tu_memclr(p_msc, sizeof(msch_interface_t));
|
|
|
|
tu_memclr(p_msc, sizeof(msch_interface_t));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
|
|
|
|
bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
|
|
|
|
{
|
|
|
|
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
msc_cbw_t const * cbw = &p_msc->cbw;
|
|
|
|
msc_cbw_t const * cbw = &p_msc->cbw;
|
|
|
|
msc_csw_t * csw = &p_msc->csw;
|
|
|
|
msc_csw_t * csw = &p_msc->csw;
|
|
|
|
|
|
|
|
|
|
|
|
switch (p_msc->stage)
|
|
|
|
switch (p_msc->stage) {
|
|
|
|
{
|
|
|
|
|
|
|
|
case MSC_STAGE_CMD:
|
|
|
|
case MSC_STAGE_CMD:
|
|
|
|
// Must be Command Block
|
|
|
|
// Must be Command Block
|
|
|
|
TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
|
|
|
|
TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
|
|
|
|
|
|
|
|
|
|
|
|
if ( cbw->total_bytes && p_msc->buffer )
|
|
|
|
if (cbw->total_bytes && p_msc->buffer) {
|
|
|
|
{
|
|
|
|
|
|
|
|
// Data stage if any
|
|
|
|
// Data stage if any
|
|
|
|
p_msc->stage = MSC_STAGE_DATA;
|
|
|
|
p_msc->stage = MSC_STAGE_DATA;
|
|
|
|
|
|
|
|
|
|
|
|
uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
|
|
|
|
uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
|
|
|
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
|
|
|
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
|
|
|
|
}else
|
|
|
|
} else {
|
|
|
|
{
|
|
|
|
|
|
|
|
// Status stage
|
|
|
|
// Status stage
|
|
|
|
p_msc->stage = MSC_STAGE_STATUS;
|
|
|
|
p_msc->stage = MSC_STAGE_STATUS;
|
|
|
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
|
|
|
|
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
|
|
|
@@ -358,10 +335,8 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
|
|
|
|
// SCSI op is complete
|
|
|
|
// SCSI op is complete
|
|
|
|
p_msc->stage = MSC_STAGE_IDLE;
|
|
|
|
p_msc->stage = MSC_STAGE_IDLE;
|
|
|
|
|
|
|
|
|
|
|
|
if (p_msc->complete_cb)
|
|
|
|
if (p_msc->complete_cb) {
|
|
|
|
{
|
|
|
|
tuh_msc_complete_data_t const cb_data = {
|
|
|
|
tuh_msc_complete_data_t const cb_data =
|
|
|
|
|
|
|
|
{
|
|
|
|
|
|
|
|
.cbw = cbw,
|
|
|
|
.cbw = cbw,
|
|
|
|
.csw = csw,
|
|
|
|
.csw = csw,
|
|
|
|
.scsi_data = p_msc->buffer,
|
|
|
|
.scsi_data = p_msc->buffer,
|
|
|
@@ -372,7 +347,8 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
|
|
|
|
break;
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
// unknown state
|
|
|
|
// unknown state
|
|
|
|
default: break;
|
|
|
|
default:
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
return true;
|
|
|
@@ -381,39 +357,35 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
// MSC Enumeration
|
|
|
|
// MSC Enumeration
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
|
|
|
|
|
static void config_get_maxlun_complete(tuh_xfer_t* xfer);
|
|
|
|
static void config_get_maxlun_complete (tuh_xfer_t* xfer);
|
|
|
|
static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
|
|
|
|
static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data);
|
|
|
|
|
|
|
|
static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
|
|
|
|
static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
|
|
|
|
static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
|
|
|
|
static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
|
|
|
|
|
|
|
|
|
|
|
|
bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
|
|
|
|
bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) {
|
|
|
|
{
|
|
|
|
|
|
|
|
(void) rhport;
|
|
|
|
(void) rhport;
|
|
|
|
TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
|
|
|
|
TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
|
|
|
|
MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol);
|
|
|
|
MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol);
|
|
|
|
|
|
|
|
|
|
|
|
// msc driver length is fixed
|
|
|
|
// msc driver length is fixed
|
|
|
|
uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
|
|
|
|
uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) +
|
|
|
|
|
|
|
|
desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
|
|
|
|
TU_ASSERT(drv_len <= max_len);
|
|
|
|
TU_ASSERT(drv_len <= max_len);
|
|
|
|
|
|
|
|
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
msch_interface_t* p_msc = get_itf(dev_addr);
|
|
|
|
tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf);
|
|
|
|
tusb_desc_endpoint_t const* ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(desc_itf);
|
|
|
|
|
|
|
|
|
|
|
|
for(uint32_t i=0; i<2; i++)
|
|
|
|
for (uint32_t i = 0; i < 2; i++) {
|
|
|
|
{
|
|
|
|
|
|
|
|
TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
|
|
|
|
TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
|
|
|
|
TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc));
|
|
|
|
TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc));
|
|
|
|
|
|
|
|
|
|
|
|
if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
|
|
|
|
if (TUSB_DIR_IN == tu_edpt_dir(ep_desc->bEndpointAddress)) {
|
|
|
|
{
|
|
|
|
|
|
|
|
p_msc->ep_in = ep_desc->bEndpointAddress;
|
|
|
|
p_msc->ep_in = ep_desc->bEndpointAddress;
|
|
|
|
}else
|
|
|
|
} else {
|
|
|
|
{
|
|
|
|
|
|
|
|
p_msc->ep_out = ep_desc->bEndpointAddress;
|
|
|
|
p_msc->ep_out = ep_desc->bEndpointAddress;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(ep_desc);
|
|
|
|
ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(ep_desc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
p_msc->itf_num = desc_itf->bInterfaceNumber;
|
|
|
|
p_msc->itf_num = desc_itf->bInterfaceNumber;
|
|
|
@@ -454,8 +426,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
|
|
|
|
return true;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void config_get_maxlun_complete (tuh_xfer_t* xfer)
|
|
|
|
static void config_get_maxlun_complete(tuh_xfer_t* xfer) {
|
|
|
|
{
|
|
|
|
|
|
|
|
uint8_t const daddr = xfer->daddr;
|
|
|
|
uint8_t const daddr = xfer->daddr;
|
|
|
|
msch_interface_t* p_msc = get_itf(daddr);
|
|
|
|
msch_interface_t* p_msc = get_itf(daddr);
|
|
|
|
|
|
|
|
|
|
|
@@ -471,18 +442,16 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
|
|
|
|
tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
|
|
|
|
tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
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static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
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{
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msc_cbw_t const* cbw = cb_data->cbw;
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msc_cbw_t const* cbw = cb_data->cbw;
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msc_csw_t const* csw = cb_data->csw;
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msc_csw_t const* csw = cb_data->csw;
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if (csw->status == 0)
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if (csw->status == 0) {
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{
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// Unit is ready, read its capacity
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// Unit is ready, read its capacity
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TU_LOG_DRV("SCSI Read Capacity\r\n");
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TU_LOG_DRV("SCSI Read Capacity\r\n");
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tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
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tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer),
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}else
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config_read_capacity_complete, 0);
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{
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} else {
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// Note: During enumeration, some device fails Test Unit Ready and require a few retries
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// Note: During enumeration, some device fails Test Unit Ready and require a few retries
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// with Request Sense to start working !!
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// with Request Sense to start working !!
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// TODO limit number of retries
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// TODO limit number of retries
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@@ -493,8 +462,7 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d
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return true;
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return true;
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}
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}
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static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
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static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
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{
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msc_cbw_t const* cbw = cb_data->cbw;
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msc_cbw_t const* cbw = cb_data->cbw;
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msc_csw_t const* csw = cb_data->csw;
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msc_csw_t const* csw = cb_data->csw;
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@@ -503,8 +471,7 @@ static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_dat
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return true;
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return true;
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}
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}
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static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
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static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
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{
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msc_cbw_t const* cbw = cb_data->cbw;
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msc_cbw_t const* cbw = cb_data->cbw;
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msc_csw_t const* csw = cb_data->csw;
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msc_csw_t const* csw = cb_data->csw;
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