change default risv-gcc to riscv-none-elf- and add _zicsr extension
add cmake for ch32v20x, skip freertos examples for CH32V20X, also skip net webserver due to lack of RAM update to use openocd with wlinke adapter
This commit is contained in:
hathach
7
hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
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7
hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
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@@ -0,0 +1,7 @@
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set(MCU_VARIANT D6)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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CH32V20x_D6
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)
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endfunction()
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109
hw/bsp/ch32v20x/family.cmake
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109
hw/bsp/ch32v20x/family.cmake
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@@ -0,0 +1,109 @@
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include_guard()
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set(CH32_FAMILY ch32v20x)
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set(SDK_DIR ${TOP}/hw/mcu/wch/${CH32_FAMILY}/EVT/EXAM/SRC)
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# include board specific
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include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
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# toolchain set up
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set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
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set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
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set(FAMILY_MCUS CH32V20X CACHE INTERNAL "")
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set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
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#------------------------------------
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# BOARD_TARGET
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#------------------------------------
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# only need to be built ONCE for all examples
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function(add_board_target BOARD_TARGET)
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if (TARGET ${BOARD_TARGET})
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return()
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endif()
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if (NOT DEFINED LD_FILE_GNU)
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set(LD_FILE_GNU ${SDK_DIR}/Ld/Link.ld)
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endif ()
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set(LD_FILE_Clang ${LD_FILE_GNU})
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if (NOT DEFINED STARTUP_FILE_GNU)
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set(STARTUP_FILE_GNU ${SDK_DIR}/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S)
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endif ()
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set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
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add_library(${BOARD_TARGET} STATIC
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${SDK_DIR}/Core/core_riscv.c
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${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
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${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
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${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
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${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
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${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
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)
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target_include_directories(${BOARD_TARGET} PUBLIC
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${SDK_DIR}/Peripheral/inc
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}
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)
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target_compile_definitions(${BOARD_TARGET} PUBLIC
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BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
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)
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update_board(${BOARD_TARGET})
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if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
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target_compile_options(${BOARD_TARGET} PUBLIC
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-mcmodel=medany
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)
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target_link_options(${BOARD_TARGET} PUBLIC
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"LINKER:--script=${LD_FILE_GNU}"
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-nostartfiles
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--specs=nosys.specs --specs=nano.specs
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)
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elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
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message(FATAL_ERROR "Clang is not supported for MSP432E4")
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elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
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target_link_options(${BOARD_TARGET} PUBLIC
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"LINKER:--config=${LD_FILE_IAR}"
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)
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endif ()
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endfunction()
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#------------------------------------
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# Functions
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#------------------------------------
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function(family_configure_example TARGET RTOS)
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family_configure_common(${TARGET} ${RTOS})
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# Board target
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add_board_target(board_${BOARD})
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#---------- Port Specific ----------
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# These files are built for each example since it depends on example's tusb_config.h
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target_sources(${TARGET} PUBLIC
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# BSP
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
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)
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target_include_directories(${TARGET} PUBLIC
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# family, hw, board
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
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)
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# Add TinyUSB target and port source
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family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X ${RTOS})
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/wch/dcd_ch32_usbfs.c
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)
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target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
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# Link dependencies
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target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
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# Flashing
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family_add_bin_hex(${TARGET})
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family_flash_openocd_wch(${TARGET})
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endfunction()
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@@ -1,3 +1,9 @@
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# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
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#CROSS_COMPILE ?= riscv32-unknown-elf-
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# Toolchain from https://nucleisys.com/download.php
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#CROSS_COMPILE ?= riscv-nuclei-elf-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
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CROSS_COMPILE ?= riscv-none-elf-
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@@ -9,23 +15,21 @@ DEPS_SUBMODULES += $(CH32V20X_SDK)
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CH32V20X_SDK_SRC = $(CH32V20X_SDK)/EVT/EXAM/SRC
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include $(TOP)/$(BOARD_PATH)/board.mk
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CPU_CORE ?= rv32imac-ilp32
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CFLAGS += \
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-march=rv32imac_zicsr \
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-mabi=ilp32 \
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-mcmodel=medany \
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-ffunction-sections \
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-fdata-sections \
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-ffat-lto-objects \
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-flto \
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-nostdlib -nostartfiles \
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-DCFG_TUSB_MCU=OPT_MCU_CH32V20X \
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-DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \
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LDFLAGS_GCC += \
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-Wl,--gc-sections \
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-specs=nosys.specs \
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-specs=nano.specs \
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-nostdlib -nostartfiles \
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--specs=nosys.specs --specs=nano.specs \
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LD_FILE = $(CH32V20X_SDK_SRC)/Ld/Link.ld
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@@ -46,5 +50,6 @@ FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
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# wch-link is not supported yet in official openOCD yet. We need to either use
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# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
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# 2. compiled from modified source https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
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OPENOCD ?= $(HOME)/app/riscv-openocd-wch/src/openocd
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flash: $(BUILD)/$(PROJECT).elf
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openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "flash write_image $<" -c reset -c exit
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$(OPENOCD) -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "flash write_image $<" -c reset -c exit
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@@ -1,4 +1,3 @@
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#interface wlink
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adapter driver wlinke
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adapter speed 6000
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transport select sdi
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@@ -11,7 +11,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TO
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set(FAMILY_MCUS CH32V307 CACHE INTERNAL "")
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set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
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set(OPENOCD_OPTION2 "-c wlink_reset_resume")
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#------------------------------------
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# BOARD_TARGET
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@@ -1,11 +1,11 @@
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# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
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#CROSS_COMPILE ?= riscv32-unknown-elf-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
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CROSS_COMPILE ?= riscv-none-embed-
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# Toolchain from https://nucleisys.com/download.php
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#CROSS_COMPILE ?= riscv-nuclei-elf-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
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#CROSS_COMPILE ?= riscv-none-elf-
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CROSS_COMPILE ?= riscv-none-elf-
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# Submodules
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CH32V307_SDK = hw/mcu/wch/ch32v307
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@@ -16,8 +16,6 @@ CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC
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include $(TOP)/$(BOARD_PATH)/board.mk
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CPU_CORE ?= rv32imac-ilp32
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# -march=rv32imac_zicsr
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CFLAGS += \
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-flto \
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-msmall-data-limit=8 \
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@@ -1,13 +1,15 @@
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#interface wlink
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adapter driver wlink
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wlink_set
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set _CHIPNAME riscv
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
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adapter driver wlinke
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adapter speed 6000
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transport select sdi
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wlink_set_address 0x00000000
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set _CHIPNAME wch_riscv
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sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
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$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
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target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
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$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
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@@ -440,6 +440,7 @@ function(family_flash_openocd TARGET)
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endfunction()
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# Add flash openocd-wch target
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# compiled from https://github.com/hathach/riscv-openocd-wch or https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
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function(family_flash_openocd_wch TARGET)
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if (NOT DEFINED OPENOCD)
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set(OPENOCD $ENV{HOME}/app/riscv-openocd-wch/src/openocd)
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@@ -1,9 +1,5 @@
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
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CROSS_COMPILE = riscv-none-embed-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
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# CROSS_COMPILE = riscv-none-elf-
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# -march=rv32i_zicsr
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CROSS_COMPILE = riscv-none-elf-
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CPU_CORE ?= rv32i-ilp32
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@@ -4,11 +4,8 @@
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# Toolchain from https://nucleisys.com/download.php
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#CROSS_COMPILE ?= riscv-nuclei-elf-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
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CROSS_COMPILE ?= riscv-none-embed-
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# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
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# CROSS_COMPILE ?= riscv-none-elf-
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CROSS_COMPILE ?= riscv-none-elf-
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# Submodules
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NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
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@@ -22,8 +19,6 @@ STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
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include $(TOP)/$(BOARD_PATH)/board.mk
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CPU_CORE ?= rv32imac-ilp32
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# -march=rv32imac_zicsr
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CFLAGS += \
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-mcmodel=medlow \
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-mstrict-align \
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