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make dwc2 stm32 rhport support dynamic

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This commit is contained in:
hathach
2022-06-03 17:24:28 +07:00
parent 2571211957
commit 31134f41a1
3 changed files with 98 additions and 62 deletions
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63
src/portable/synopsys/dwc2/dwc2_stm32.h
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@@ -56,12 +56,9 @@
#define EP_FIFO_SIZE_FS 4096
#define EP_MAX_HS 9
#define EP_FIFO_SIZE_HS 4096
#if (! defined USB2_OTG_FS)
// H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
// USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
#define USB_OTG_FS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
#define OTG_FS_IRQn OTG_HS_IRQn
#endif
// NOTE: H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
// USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
#include "stm32f7xx.h"
@@ -79,35 +76,57 @@
#error "Unsupported MCUs"
#endif
// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
#if TUD_OPT_RHPORT == 0
#define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE
#define DWC2_EP_MAX EP_MAX_FS
#define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_FS
#define RHPORT_IRQn OTG_FS_IRQn
// OTG HS always has higher number of endpoints than FS
#ifdef EP_MAX_HS
#define DWC2_EP_MAX EP_MAX_HS
#else
#define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE
#define DWC2_EP_MAX EP_MAX_HS
#define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_HS
#define RHPORT_IRQn OTG_HS_IRQn
#define DWC2_EP_MAX EP_MAX_FS
#endif
// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
//#if TUD_OPT_RHPORT == 0
// #define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE
// #define DWC2_EP_MAX EP_MAX_FS
// #define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_FS
// #define RHPORT_IRQn OTG_FS_IRQn
//
//#else
// #define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE
// #define DWC2_EP_MAX EP_MAX_HS
// #define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_HS
// #define RHPORT_IRQn OTG_HS_IRQn
//
//#endif
// On STM32 for consistency we associate
// - Port0 to OTG_FS, and Port1 to OTG_HS
static const dwc2_controller_t _dwc2_controller[] =
{
#ifdef USB_OTG_FS_PERIPH_BASE
{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS},
#endif
#ifdef USB_OTG_HS_PERIPH_BASE
{ .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS},
#endif
};
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
extern uint32_t SystemCoreClock;
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_enable(uint8_t rhport)
{
(void) rhport;
NVIC_EnableIRQ(RHPORT_IRQn);
NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_disable (uint8_t rhport)
{
(void) rhport;
NVIC_DisableIRQ(RHPORT_IRQn);
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE