Use DMA enable for DCache condition

Signed-off-by: HiFiPhile <admin@hifiphile.com>
This commit is contained in:
HiFiPhile
2025-07-05 12:35:47 +02:00
parent ffab23cf0f
commit 3287cfaf76
6 changed files with 18 additions and 29 deletions

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@@ -220,8 +220,9 @@
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
#endif #endif
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 // Enable dcache if DMA is enabled
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
#elif TU_CHECK_MCU(OPT_MCU_STM32H7) #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -232,8 +233,9 @@
#define TUP_DCD_ENDPOINT_MAX 9 #define TUP_DCD_ENDPOINT_MAX 9
#if __CORTEX_M == 7 #if __CORTEX_M == 7
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 // Enable dcache if DMA is enabled
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
#endif #endif
@@ -333,8 +335,9 @@
// MCU with on-chip HS Phy // MCU with on-chip HS Phy
#define TUP_RHPORT_HIGHSPEED 1 #define TUP_RHPORT_HIGHSPEED 1
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 // Enable dcache if DMA is enabled
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+

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@@ -36,39 +36,39 @@
#endif #endif
//------------- Device DCache declaration -------------// //------------- Device DCache declaration -------------//
#define TUD_EPBUF_DCACHE_SIZE(_size) (TUD_EPBUF_DCACHE_ALIGNED ? \ #define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
(TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size)) (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
// Declare an endpoint buffer with uint8_t[size] // Declare an endpoint buffer with uint8_t[size]
#define TUD_EPBUF_DEF(_name, _size) \ #define TUD_EPBUF_DEF(_name, _size) \
union { \ union { \
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \ CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \ TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
} }
// Declare an endpoint buffer with a type // Declare an endpoint buffer with a type
#define TUD_EPBUF_TYPE_DEF(_type, _name) \ #define TUD_EPBUF_TYPE_DEF(_type, _name) \
union { \ union { \
CFG_TUD_MEM_ALIGN _type _name; \ CFG_TUD_MEM_ALIGN _type _name; \
TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
} }
//------------- Host DCache declaration -------------// //------------- Host DCache declaration -------------//
#define TUH_EPBUF_DCACHE_SIZE(_size) (TUH_EPBUF_DCACHE_ALIGNED ? \ #define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
(TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size)) (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))
// Declare an endpoint buffer with uint8_t[size] // Declare an endpoint buffer with uint8_t[size]
#define TUH_EPBUF_DEF(_name, _size) \ #define TUH_EPBUF_DEF(_name, _size) \
union { \ union { \
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \ CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \ TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
} }
// Declare an endpoint buffer with a type // Declare an endpoint buffer with a type
#define TUH_EPBUF_TYPE_DEF(_type, _name) \ #define TUH_EPBUF_TYPE_DEF(_type, _name) \
union { \ union { \
CFG_TUH_MEM_ALIGN _type _name; \ CFG_TUH_MEM_ALIGN _type _name; \
TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
} }

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@@ -88,7 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc
//-------------------------------------------------------------------- //--------------------------------------------------------------------
// DMA // DMA
//-------------------------------------------------------------------- //--------------------------------------------------------------------
#if CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE #if CFG_TUD_MEM_DCACHE_ENABLE
bool dcd_dcache_clean(const void* addr, uint32_t data_size) { bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size); TU_VERIFY(addr && data_size);
return dwc2_dcache_clean(addr, data_size); return dwc2_dcache_clean(addr, data_size);

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@@ -280,7 +280,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
} }
//------------- DCache -------------// //------------- DCache -------------//
#if (CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE) || (CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE) #if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
typedef struct typedef struct
{ {

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@@ -141,7 +141,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA; return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA;
} }
#if CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE #if CFG_TUH_MEM_DCACHE_ENABLE
bool hcd_dcache_clean(const void* addr, uint32_t data_size) { bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size); TU_VERIFY(addr && data_size);
return dwc2_dcache_clean(addr, data_size); return dwc2_dcache_clean(addr, data_size);

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@@ -465,13 +465,6 @@
#define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
#endif #endif
#if CFG_TUD_MEM_DCACHE_ENABLE && \
(CFG_TUD_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
#define TUD_EPBUF_DCACHE_ALIGNED 1
#else
#define TUD_EPBUF_DCACHE_ALIGNED 0
#endif
#ifndef CFG_TUD_ENDPOINT0_SIZE #ifndef CFG_TUD_ENDPOINT0_SIZE
#define CFG_TUD_ENDPOINT0_SIZE 64 #define CFG_TUD_ENDPOINT0_SIZE 64
#endif #endif
@@ -591,13 +584,6 @@
#define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
#endif #endif
#if CFG_TUH_MEM_DCACHE_ENABLE && \
(CFG_TUH_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
#define TUH_EPBUF_DCACHE_ALIGNED 1
#else
#define TUH_EPBUF_DCACHE_ALIGNED 0
#endif
//------------- CLASS -------------// //------------- CLASS -------------//
#ifndef CFG_TUH_HUB #ifndef CFG_TUH_HUB