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fix trailing space and new line

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temporarily disable codespell
This commit is contained in:
hathach
2023-03-17 16:12:49 +07:00
parent 2faad42cb1
commit 3623ba1884
581 changed files with 2553 additions and 2694 deletions
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78
src/portable/bridgetek/ft9xx/dcd_ft9xx.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright 2021 Bridgetek Pte Ltd
@@ -24,15 +24,15 @@
* This file is part of the TinyUSB stack.
*/
/*
* Contains code adapted from Bridgetek Pte Ltd via license terms stated
/*
* Contains code adapted from Bridgetek Pte Ltd via license terms stated
* in https://brtchip.com/BRTSourceCodeLicenseAgreement
*/
#include "tusb_option.h"
#if CFG_TUD_ENABLED && \
(CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X)
(CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X)
#include <stdint.h>
#include <ft900.h>
@@ -58,7 +58,7 @@ struct ft9xx_xfer_state
{
volatile uint8_t ready; // OUT Transfer has been received and waiting for transfer.
volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
int16_t total_size; // Total transfer size in bytes for this transfer.
int16_t remain_size; // Total remaining in transfer.
uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
@@ -92,7 +92,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
// Manage an OUT transfer from the host.
// This can be up-to the maximum packet size of the endpoint.
// Continuation of a transfer beyond the maximum packet size is performed
// Continuation of a transfer beyond the maximum packet size is performed
// by the interrupt handler.
static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
{
@@ -125,7 +125,7 @@ static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_
// Manage an IN transfer to the host.
// This can be up-to the maximum packet size of the endpoint.
// Continuation of a transfer beyond the maximum packet size is performed
// Continuation of a transfer beyond the maximum packet size is performed
// by the interrupt handler.
static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
{
@@ -196,7 +196,7 @@ static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
return xfer_bytes;
}
// Reset all non-control endpoints to a default state.
// Reset all non-control endpoints to a default state.
// Control endpoint is always enabled and ready. All others disabled.
static void _ft9xx_reset_edpts(void)
{
@@ -208,7 +208,7 @@ static void _ft9xx_reset_edpts(void)
// Disable hardware.
USBD_EP_CR_REG(i) = 0;
}
// Enable interrupts from USB device control.
USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
}
@@ -319,7 +319,7 @@ static void _dcd_ft9xx_detach(void)
}
// Determine the speed of the USB to which we are connected.
// Set the speed of the PHY accordingly.
// Set the speed of the PHY accordingly.
// High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings.
static void _ft9xx_usb_speed(void)
{
@@ -379,16 +379,16 @@ static void _ft9xx_usb_speed(void)
}
// Send a buffer to the USB IN FIFO.
// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data
// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data
// to the FIFO using the most efficient MCU streamout combination.
// If streaming is disabled then it will send each byte of the buffer in turn
// If streaming is disabled then it will send each byte of the buffer in turn
// to the FIFO. The is no reason to not stream.
// The total number of bytes sent to the FIFO is returned.
static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
{
uint16_t bytes_read = 0;
uint16_t buff_size = length;
#ifdef USBD_USE_STREAMS
volatile uint8_t *data_reg;
@@ -423,7 +423,7 @@ static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
bytes_read = buff_size;
}
#else // USBD_USE_STREAMS
bytes_read = buff_size;
while (buff_size--)
{
@@ -438,7 +438,7 @@ static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
// Receive a buffer from the USB OUT FIFO.
// When the macro USBD_USE_STREAMS is defined this will stream from the FIFO
// to a buffer of data using the most efficient MCU streamin combination.
// If streaming is disabled then it will receive each byte from the FIFO in turn
// If streaming is disabled then it will receive each byte from the FIFO in turn
// to the buffer. The is no reason to not stream.
// The total number of bytes received from the FIFO is returned.
static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
@@ -448,7 +448,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
#endif // USBD_USE_STREAMS
uint16_t bytes_read = 0;
uint16_t buff_size = length;
if (length > 0)
{
if (ep_number == USBD_EP_0)
@@ -596,7 +596,7 @@ void dcd_remote_wakeup(uint8_t rhport)
SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
// At least 2 ms of delay needed for RESUME Data K state.
delayms(2);
delayms(2);
SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
@@ -621,7 +621,7 @@ void dcd_connect(uint8_t rhport)
// Determine bus speed and signal speed to tusb.
_ft9xx_usb_speed();
}
// Setup the control endpoint only.
#if CFG_TUD_ENDPOINT0_SIZE == 64
USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
@@ -702,7 +702,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
TU_LOG1("FT9xx endpoint size not valid: requested %d max 1024\r\n", ep_size);
return false;
}
// Calculate actual amount of buffer RAM used by this endpoint. This may be more than the
// Calculate actual amount of buffer RAM used by this endpoint. This may be more than the
// requested size.
ep_buff_size = 8 << ep_reg_size;
@@ -714,7 +714,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED)
{
// This could be because an endpoint has been assigned with the same number.
// On FT9xx, IN and OUT endpoints may not have the same number. e.g. There
// On FT9xx, IN and OUT endpoints may not have the same number. e.g. There
// cannot been an 0x81 and 0x01 endpoint.
TU_LOG1("FT9xx endpoint %d already assigned\r\n", ep_number);
return false;
@@ -723,7 +723,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
// Check that there is enough buffer RAM to allocate to this new endpoint.
// Available buffer RAM depends on the device revision.
// The IN and OUT buffer RAM should be the same size.
if (ep_dir == USBD_DIR_IN)
if (ep_dir == USBD_DIR_IN)
total_ram = USBD_RAMTOTAL_IN;
else
total_ram = USBD_RAMTOTAL_OUT;
@@ -753,7 +753,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
if (total_ram < ep_buff_size)
{
TU_LOG1("FT9xx insufficient buffer RAM for endpoint %d\r\n", ep_number);
return false;
return false;
}
// Set the type of this endpoint in the control register.
@@ -827,7 +827,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
ep_xfer[ep_number].total_size = total_bytes;
ep_xfer[ep_number].remain_size = total_bytes;
ep_xfer[ep_number].buff_ptr = buffer;
if (ep_number == USBD_EP_0)
{
ep_xfer[USBD_EP_0].dir = ep_dir;
@@ -876,7 +876,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
// then report the transfer complete with dcd_event_xfer_complete.
ep_xfer[ep_number].valid = 1;
}
}
}
status = true;
}
else
@@ -922,7 +922,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
CRITICAL_SECTION_END
}
// Clear stall (non-control endpoint), data toggle is also reset to DATA0
// Clear stall (non-control endpoint), data toggle is also reset to DATA0
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
{
uint8_t ep_number = tu_edpt_number(ep_addr);
@@ -1025,7 +1025,7 @@ void dcd_int_handler(uint8_t rhport)
// Host has sent a SETUP packet. Receive this into the SETUP packet store.
_ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request));
// Send the packet to tinyusb.
dcd_event_setup_received(BOARD_TUD_RHPORT, _ft9xx_setup_packet, true);
@@ -1046,13 +1046,13 @@ void dcd_int_handler(uint8_t rhport)
{
xfer_bytes = (uint16_t)ep_xfer[USBD_EP_0].total_size;
// Transfer incoming data from an OUT packet to the buffer supplied.
// Transfer incoming data from an OUT packet to the buffer supplied.
if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT)
{
xfer_bytes = _ft9xx_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
}
// Now signal completion of data packet.
dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0),
dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0),
xfer_bytes, XFER_RESULT_SUCCESS, true);
// Incoming FIFO has been cleared.
@@ -1097,13 +1097,13 @@ void dcd_int_handler(uint8_t rhport)
// Start or continue an OUT transfer.
if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
{
xfer_bytes = _ft9xx_edpt_xfer_out(ep_number,
ep_xfer[ep_number].buff_ptr,
xfer_bytes = _ft9xx_edpt_xfer_out(ep_number,
ep_xfer[ep_number].buff_ptr,
(uint16_t)ep_xfer[ep_number].remain_size);
// Report each OUT packet received to the stack.
dcd_event_xfer_complete(BOARD_TUD_RHPORT,
ep_number /* | TUSB_DIR_OUT_MASK */,
dcd_event_xfer_complete(BOARD_TUD_RHPORT,
ep_number /* | TUSB_DIR_OUT_MASK */,
xfer_bytes, XFER_RESULT_SUCCESS, true);
ep_xfer[ep_number].buff_ptr += xfer_bytes;
@@ -1114,8 +1114,8 @@ void dcd_int_handler(uint8_t rhport)
{
if (ep_xfer[ep_number].remain_size > 0)
{
xfer_bytes = _ft9xx_edpt_xfer_in(ep_number,
ep_xfer[ep_number].buff_ptr,
xfer_bytes = _ft9xx_edpt_xfer_in(ep_number,
ep_xfer[ep_number].buff_ptr,
(uint16_t)ep_xfer[ep_number].remain_size);
ep_xfer[ep_number].buff_ptr += xfer_bytes;
@@ -1124,8 +1124,8 @@ void dcd_int_handler(uint8_t rhport)
if (ep_xfer[ep_number].remain_size == 0)
{
dcd_event_xfer_complete(BOARD_TUD_RHPORT,
ep_number | TUSB_DIR_IN_MASK,
dcd_event_xfer_complete(BOARD_TUD_RHPORT,
ep_number | TUSB_DIR_IN_MASK,
ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
}
}
@@ -1151,7 +1151,7 @@ void dcd_int_handler(uint8_t rhport)
// once the transfer is initiated.
// Strictly this should not happen for a non-control endpoint. Interrupts
// are disabled when there are no transfers setup for an endpoint.
ep_xfer[ep_number].ready = 1;
ep_xfer[ep_number].ready = 1;
}
}
}
@@ -1159,13 +1159,13 @@ void dcd_int_handler(uint8_t rhport)
}
}
// Power management interrupt handler.
// Power management interrupt handler.
// This handles USB device related power management interrupts only.
void ft9xx_usbd_pm_ISR(void)
{
uint16_t pmcfg = SYS->PMCFG_H;
// Main interrupt handler is responible for
// Main interrupt handler is responible for
if (pmcfg & MASK_SYS_PMCFG_DEV_CONN_DEV)
{
// Signal connection interrupt

2
src/portable/chipidea/ci_hs/ci_hs_type.h
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)

2
src/portable/chipidea/ci_hs/dcd_ci_hs.c
View File

@@ -545,7 +545,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
}
}
// only number of bytes in the IOC qtd
dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
}

2
src/portable/chipidea/ci_hs/hcd_ci_hs.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

6
src/portable/ehci/ehci.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -566,7 +566,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
case EHCI_QTYPE_ITD: // TODO support hs/fs ISO
case EHCI_QTYPE_SITD:
case EHCI_QTYPE_FSTN:
default: break;
}
@@ -683,7 +683,7 @@ void hcd_int_handler(uint8_t rhport)
uint32_t int_status = regs->status;
int_status &= regs->inten;
regs->status = int_status; // Acknowledge handled interrupt
if (int_status == 0) return;

1
src/portable/espressif/esp32sx/dcd_esp32sx.c
View File

@@ -874,4 +874,3 @@ void dcd_int_disable (uint8_t rhport)
}
#endif // #if OPT_MCU_ESP32S2 || OPT_MCU_ESP32S3

8
src/portable/mentor/musb/dcd_musb.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Koji KITAYAMA
@@ -572,7 +572,7 @@ static void process_bus_reset(uint8_t rhport)
_dcd.pipe0.buf = NULL;
USB0->TXIE = 1; /* Enable only EP0 */
USB0->RXIE = 0;
USB0->RXIE = 0;
/* Clear FIFO settings */
for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
@@ -722,7 +722,7 @@ void dcd_edpt_close_all(uint8_t rhport)
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
NVIC_DisableIRQ(USB0_IRQn);
USB0->TXIE = 1; /* Enable only EP0 */
USB0->RXIE = 0;
USB0->RXIE = 0;
for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
regs->TXMAXP = 0;
regs->TXCSRH = 0;
@@ -854,7 +854,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
if (tu_edpt_dir(ep_addr)) { /* IN */
regs->TXCSRL = USB_TXCSRL1_CLRDT;
} else { /* OUT */
regs->RXCSRL = USB_RXCSRL1_CLRDT;
regs->RXCSRL = USB_RXCSRL1_CLRDT;
}
if (ie) NVIC_EnableIRQ(USB0_IRQn);
}

4
src/portable/mentor/musb/hcd_musb.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Koji KITAYAMA
@@ -588,7 +588,7 @@ void hcd_int_disable(uint8_t rhport)
uint32_t hcd_frame_number(uint8_t rhport)
{
(void)rhport;
/* The device must be reset at least once after connection
/* The device must be reset at least once after connection
* in order to start the frame counter. */
if (_hcd.need_reset) hcd_port_reset(rhport);
return USB0->FRAME;

4
src/portable/microchip/pic/dcd_pic.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Koji Kitayama
@@ -486,7 +486,7 @@ void dcd_init(uint8_t rhport)
#else
U1PWRCbits.USBPWR = 1;
#endif
#if TU_PIC_INT_SIZE == 4
uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);

40
src/portable/microchip/pic32mz/usbhs_registers.h
View File

@@ -21,7 +21,7 @@
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*******************************************************************************/
/*******************************************************************************
USBHS Peripheral Library Register Definitions
USBHS Peripheral Library Register Definitions
File Name:
usbhs_registers.h
@@ -50,16 +50,16 @@
#define USBHS_REG_INTRRX 0x004
#define USBHS_REG_INTRTXE 0x006
#define USBHS_REG_INTRRXE 0x008
#define USBHS_REG_INTRUSB 0x00A
#define USBHS_REG_INTRUSBE 0x00B
#define USBHS_REG_INTRUSB 0x00A
#define USBHS_REG_INTRUSBE 0x00B
#define USBHS_REG_FRAME 0x00C
#define USBHS_REG_INDEX 0x00E
#define USBHS_REG_TESTMODE 0x00F
/*******************************************************
* Endpoint Control Status Registers (CSR). These values
* Endpoint Control Status Registers (CSR). These values
* should be added to either the 0x10 to access the
* register through Indexed CSR. To access the actual
* register through Indexed CSR. To access the actual
* CSR, see ahead in this header file.
******************************************************/
@@ -99,20 +99,20 @@
#define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
/* FADDR - Device Function Address */
typedef union
typedef union
{
struct __attribute__((packed))
struct __attribute__((packed))
{
unsigned FUNC:7;
unsigned :1;
};
uint8_t w;
uint8_t w;
} __USBHS_FADDR_t;
/* POWER - Control Resume and Suspend signalling */
typedef union
typedef union
{
struct __attribute__((packed))
{
@@ -126,14 +126,14 @@ typedef union
unsigned ISOUPD:1;
};
struct
{
{
uint8_t w;
};
} __USBHS_POWER_t;
/* INTRTXE - Transmit endpoint interrupt enable */
typedef union
typedef union
{
struct __attribute__((packed))
{
@@ -155,7 +155,7 @@ typedef union
} __USBHS_INTRTXE_t;
/* INTRRXE - Receive endpoint interrupt enable */
typedef union
typedef union
{
struct __attribute__((packed))
{
@@ -198,7 +198,7 @@ typedef union
} __USBHS_INTRUSBE_t;
/* FRAME - Frame number */
typedef union
typedef union
{
struct __attribute__((packed))
{
@@ -213,7 +213,7 @@ typedef union
} __USBHS_FRAME_t;
/* INDEX - Endpoint index */
typedef union
typedef union
{
struct __attribute__((packed))
{
@@ -228,7 +228,7 @@ typedef union
} __USBHS_INDEX_t;
/* TESTMODE - Test mode register */
typedef union
typedef union
{
struct __attribute__((packed))
{
@@ -248,7 +248,7 @@ typedef union
} __USBHS_TESTMODE_t;
/* COUNT0 - Indicates the amount of data received in endpoint 0 */
/* COUNT0 - Indicates the amount of data received in endpoint 0 */
typedef union
{
struct __attribute__((packed))
@@ -627,7 +627,7 @@ typedef union
};
uint16_t w;
} __USBHS_TXMAXP_t;
} __USBHS_TXMAXP_t;
/* TXFIFOSZ - Size of the transmit endpoint FIFO */
typedef struct __attribute__((packed))
@@ -781,7 +781,7 @@ typedef union
} __USBHS_DMACNTL_t;
/* Endpoint Control and Status Register Set */
/* Endpoint Control and Status Register Set */
typedef struct __attribute__((packed))
{
volatile __USBHS_TXMAXP_t TXMAXPbits;
@@ -906,7 +906,7 @@ typedef struct __attribute__((aligned(4),packed))
volatile __USBHS_TXFIFOADD_t TXFIFOADDbits;
volatile __USBHS_RXFIFOADD_t RXFIFOADDbits;
volatile uint32_t VCONTROL;
volatile uint16_t HWVERS;
volatile uint8_t padding1[10];
@@ -923,7 +923,7 @@ typedef struct __attribute__((aligned(4),packed))
volatile __USBHS_TARGET_ADDR_t TADDR[16];
volatile __USBHS_EPCSR_t EPCSR[16];
volatile uint32_t DMA_INTR;
volatile __USBHS_DMA_CHANNEL_t DMA_CHANNEL[8];
volatile __USBHS_DMA_CHANNEL_t DMA_CHANNEL[8];
volatile uint32_t RQPKTXOUNT[16];
} usbhs_registers_t;

2
src/portable/microchip/samg/dcd_samg.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)

6
src/portable/microchip/samx7x/common_usb_regs.h
View File

@@ -2007,7 +2007,7 @@
/** \brief DEVDMA hardware registers */
typedef struct
{
{
__IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */
__IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */
__IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */
@@ -2016,7 +2016,7 @@ typedef struct
/** \brief HSTDMA hardware registers */
typedef struct
{
{
__IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */
__IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */
__IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */
@@ -2025,7 +2025,7 @@ typedef struct
/** \brief USBHS hardware registers */
typedef struct
{
{
__IO uint32_t DEVCTRL; /**< (USBHS Offset: 0x00) Device General Control Register */
__I uint32_t DEVISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */
__O uint32_t DEVICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */

36
src/portable/microchip/samx7x/dcd_samx7x.c
View File

@@ -241,7 +241,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
if (int_status & DEVEPTISR_RXOUTI)
{
uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
if (count && xfer->total_len)
{
uint16_t remain = xfer->total_len - xfer->queued_len;
@@ -252,7 +252,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
if (xfer->buffer)
{
memcpy(xfer->buffer + xfer->queued_len, ptr, count);
} else
} else
{
tu_fifo_write_n(xfer->fifo, ptr, count);
}
@@ -281,7 +281,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
{
// TX not complete
dcd_transmit_packet(xfer, 0);
} else
} else
{
// TX complete
dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -292,7 +292,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
}
}
}
} else
} else
{
if (int_status & DEVEPTISR_RXOUTI)
{
@@ -333,7 +333,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
{
// TX not complete
dcd_transmit_packet(xfer, ep_ix);
} else
} else
{
// TX complete
dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -359,7 +359,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
{
dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
} else
} else
{
dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
}
@@ -507,12 +507,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
// Enable Endpoint 0 Interrupts
USB_REG->DEVIER = DEVIER_PEP_0;
return true;
} else
} else
{
// Endpoint configuration is not successful
return false;
}
} else
} else
{
// Enable the endpoint
USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
@@ -544,7 +544,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
{
USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
return true;
} else
} else
{
// Endpoint configuration is not successful
return false;
@@ -583,7 +583,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
{
memcpy(ptr, xfer->buffer + xfer->queued_len, len);
}
else
else
{
tu_fifo_read_n(xfer->fifo, ptr, len);
}
@@ -595,7 +595,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
{
// Control endpoint: clear the interrupt flag to send the data
USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
} else
} else
{
// Other endpoint types: clear the FIFO control flag to send the data
USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
@@ -616,7 +616,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
xfer->total_len = total_bytes;
xfer->queued_len = 0;
xfer->fifo = NULL;
if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
{
// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
@@ -648,12 +648,12 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
// and the DMA transfer must be not started.
// It is the end of transfer
return false;
} else
} else
{
if (dir == TUSB_DIR_OUT)
{
USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
} else
} else
{
dcd_transmit_packet(xfer,epnum);
}
@@ -701,20 +701,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
// Clean invalidate cache of linear part
CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin;
if (info.len_wrap)
{
// Clean invalidate cache of wrapped part
CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
dma_desc[epnum - 1].next_desc = 0;
dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
dma_desc[epnum - 1].chnl_ctrl =
udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos);
// Clean cache of wrapped DMA descriptor
CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
} else {
@@ -743,7 +743,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
if (dir == TUSB_DIR_OUT)
{
USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
} else
} else
{
dcd_transmit_packet(xfer,epnum);
}

2
src/portable/nordic/nrf5x/dcd_nrf5x.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

6
src/portable/nuvoton/nuc120/dcd_nuc120.c
View File

@@ -27,9 +27,9 @@
/*
Theory of operation:
The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex,
so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for
The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex,
so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for
EP0_IN and EP0_OUT respectively. This leaves up to four for user usage.
*/

6
src/portable/nuvoton/nuc121/dcd_nuc121.c
View File

@@ -27,9 +27,9 @@
/*
Theory of operation:
The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex,
so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for
The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex,
so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for
EP0_IN and EP0_OUT respectively. This leaves up to six for user usage.
*/

6
src/portable/nuvoton/nuc505/dcd_nuc505.c
View File

@@ -27,9 +27,9 @@
/*
Theory of operation:
The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition
The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition
to dedicated support for the control endpoint (EP0). The non-user endpoints
are referred to as "user" EPs in this code, and follow the datasheet
are referred to as "user" EPs in this code, and follow the datasheet
nomenclature of EPA through EPL.
*/
@@ -389,7 +389,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
while (total_bytes < USBD->CEPRXCNT);
for (int count = 0; count < total_bytes; count++)
*buffer++ = USBD->CEPDAT_BYTE;
dcd_event_xfer_complete(0, ep_addr, total_bytes, XFER_RESULT_SUCCESS, true);
}
}

6
src/portable/nxp/khci/dcd_khci.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Koji Kitayama
@@ -296,7 +296,7 @@ void dcd_int_disable(uint8_t rhport)
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
_dcd.addr = dev_addr & 0x7F;
_dcd.addr = dev_addr & 0x7F;
/* Response with status first before changing device address */
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
}
@@ -528,7 +528,7 @@ void dcd_int_handler(uint8_t rhport)
if (is & USB_ISTAT_SLEEP_MASK) {
// TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
// Note Host usually has extra delay after bus reset (without SOF), which could falsely
// Note Host usually has extra delay after bus reset (without SOF), which could falsely
// detected as Sleep event. Though usbd has debouncing logic so we are good
KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
process_bus_sleep(rhport);

4
src/portable/nxp/khci/hcd_khci.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Koji Kitayama
@@ -414,7 +414,7 @@ void hcd_int_disable(uint8_t rhport)
uint32_t hcd_frame_number(uint8_t rhport)
{
(void)rhport;
/* The device must be reset at least once after connection
/* The device must be reset at least once after connection
* in order to start the frame counter. */
if (_hcd.need_reset) hcd_port_reset(rhport);
uint32_t frmnum = KHCI->FRMNUML;

2
src/portable/nxp/lpc17_40/dcd_lpc17_40.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

2
src/portable/nxp/lpc17_40/dcd_lpc17_40.h
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

3
src/portable/nxp/lpc17_40/hcd_lpc17_40.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -44,4 +44,3 @@ void hcd_int_disable(uint8_t rhport)
}
#endif

7
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -373,7 +373,7 @@ void dcd_edpt_close_all (uint8_t rhport)
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
uint8_t ep_id = ep_addr2id(ep_addr);
_dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
_dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
@@ -426,7 +426,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
static void bus_reset(uint8_t rhport)
{
tu_memclr(&_dcd, sizeof(dcd_data_t));
edpt_reset_all(rhport);
edpt_reset_all(rhport);
// disable all endpoints as specified by LPC55S69 UM Table 778
for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
@@ -575,4 +575,3 @@ void dcd_int_handler(uint8_t rhport)
}
#endif

2
src/portable/nxp/transdimension/common_transdimension.h
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)

2
src/portable/nxp/transdimension/dcd_transdimension.c
View File

@@ -569,7 +569,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
}
}
// only number of bytes in the IOC qtd
dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
}

2
src/portable/nxp/transdimension/hcd_transdimension.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

3
src/portable/ohci/ohci.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -715,4 +715,3 @@ void hcd_int_handler(uint8_t hostid)
#endif

2
src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)

2
src/portable/raspberrypi/rp2040/rp2040_usb.h
View File

@@ -47,7 +47,7 @@ typedef struct hw_endpoint
{
// Is this a valid struct
bool configured;
// Transfer direction (i.e. IN is rx for host but tx for device)
// allows us to common up transfer functions
bool rx;

45
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Nathan Conrad
@@ -181,7 +181,7 @@ static void dcd_handle_bus_reset(void);
static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
static void dcd_ep_ctr_handler(void);
// PMA allocation/access
// PMA allocation/access
static uint8_t open_ep_count;
static uint16_t ep_buf_ptr; ///< Points to first free memory location
static void dcd_pma_alloc_reset(void);
@@ -249,7 +249,7 @@ void dcd_init (uint8_t rhport)
asm("NOP");
}
USB->CNTR = 0; // Enable USB
USB->BTABLE = DCD_STM32_BTABLE_BASE;
USB->ISTR = 0; // Clear pending interrupts
@@ -263,7 +263,7 @@ void dcd_init (uint8_t rhport)
USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
dcd_handle_bus_reset();
// Enable pull-up if supported
if ( dcd_connect ) dcd_connect(rhport);
}
@@ -464,12 +464,12 @@ static void dcd_handle_bus_reset(void)
//__IO uint16_t * const epreg = &(EPREG(0));
USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
{
// Clear all EPREG (or maybe this is automatic? I'm not sure)
pcd_set_endpoint(USB,i,0u);
// Clear EP allocation status
ep_alloc_status[i].ep_num = 0xFF;
ep_alloc_status[i].ep_type = 0xFF;
@@ -531,7 +531,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
{
return;
}
if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
{
// The setup_received function uses memcpy, so this must first copy the setup data into
@@ -743,11 +743,11 @@ static void dcd_pma_alloc_reset(void)
/***
* Allocate a section of PMA
*
*
* If the EP number has already been allocated, and the new allocation
* is larger than the old allocation, then this will fail with a TU_ASSERT.
* (This is done to simplify the code. More complicated algorithms could be used)
*
*
* During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
*/
static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
@@ -838,7 +838,7 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
ep_alloc_status[i].ep_num = epnum;
ep_alloc_status[i].ep_type = ep_type;
ep_alloc_status[i].allocated[dir] = true;
return i;
}
}
@@ -860,7 +860,7 @@ static void dcd_ep_free(uint8_t ep_addr)
for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
{
// Check if EP number & dir are the same
if(ep_alloc_status[i].ep_num == epnum &&
if(ep_alloc_status[i].ep_num == epnum &&
ep_alloc_status[i].allocated[dir] == dir)
{
ep_alloc_status[i].allocated[dir] = false;
@@ -968,9 +968,9 @@ void dcd_edpt_close_all (uint8_t rhport)
/**
* Close an endpoint.
*
*
* This function may be called with interrupts enabled or disabled.
*
*
* This also clears transfers in progress, should there be any.
*/
void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
@@ -998,9 +998,9 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
{
(void)rhport;
TU_ASSERT(largest_packet_size <= 1024);
uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
@@ -1011,10 +1011,10 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
*pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr;
*pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr;
return true;
}
@@ -1035,7 +1035,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo
{
pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
}
pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
// Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
// or being double-buffered (bulk endpoints)
@@ -1250,11 +1250,11 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
{
// Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
tu_fifo_buffer_info_t info;
tu_fifo_get_read_info(ff, &info);
tu_fifo_get_read_info(ff, &info);
uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin);
uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
// We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
// last lin byte will be combined with wrapped part
// To ensure PMA is always access 16bit aligned (dst aligned to 16 bit)
@@ -1352,7 +1352,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
// Copy last linear byte & first wrapped byte
uint16_t tmp;
dcd_read_packet_memory(&tmp, src, 2);
((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp;
((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U);
src += 2;
@@ -1379,4 +1379,3 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
}
#endif

672
src/portable/st/synopsys/synopsys_common.h
View File

File diff suppressed because it is too large Load Diff

6
src/portable/sunxi/dcd_sunxi_musb.c
View File

@@ -996,7 +996,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
if (dir_in) {
USBC_Writew(mps, USBC_REG_TXMAXP(USBC0_BASE));
reg_val = (1 << USBC_BP_TXCSR_D_MODE)
reg_val = (1 << USBC_BP_TXCSR_D_MODE)
| (1 << USBC_BP_TXCSR_D_FLUSH_FIFO)
| (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE);
if (xfer == TUSB_XFER_ISOCHRONOUS)
@@ -1048,7 +1048,7 @@ void dcd_edpt_close_all(uint8_t rhport)
USBC_REG_TXCSR(USBC0_BASE));
USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
USBC_REG_RXCSR(USBC0_BASE));
USBC_Writew(0, USBC_REG_TXFIFOAD(USBC0_BASE));
@@ -1078,7 +1078,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
} else {
USBC_INT_DisableRxEp(epn);
USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
USBC_REG_RXCSR(USBC0_BASE));
USBC_Writew(0, USBC_REG_RXFIFOAD(USBC0_BASE));

2
src/portable/template/dcd_template.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)

2
src/portable/valentyusb/eptri/dcd_eptri.c
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

2
src/portable/valentyusb/eptri/dcd_eptri.h
View File

@@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)

8
src/portable/wch/ch32v307/dcd_usbhs.c
View File

@@ -1,7 +1,7 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2022 Greg Davill
* Copyright (c) 2022 Greg Davill
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -261,7 +261,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
USBHS_Dev_Endp0_Tog ^= 1;
} else {
xfer->queued_len += short_packet_size;
EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
EP_TX_LEN(epnum) = short_packet_size;
@@ -366,7 +366,7 @@ void dcd_int_handler(uint8_t rhport) {
} else if (intflag & USBHS_SETUP_FLAG) {
USBHS_Dev_Endp0_Tog = 1;
dcd_event_setup_received(0, EP0_DatabufHD, true);
USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
} else if (intflag & USBHS_DETECT_FLAG) {
USBHS_Dev_Endp0_Tog = 1;