hw/h7rs: Enable D-Cache in BSP

Signed-off-by: HiFiPhile <admin@hifiphile.com>
This commit is contained in:
HiFiPhile
2025-01-25 13:02:08 +01:00
parent e19ff3ecae
commit 37316e057d
3 changed files with 14 additions and 0 deletions

View File

@@ -78,6 +78,11 @@ void OTG_HS_IRQHandler(void) {
//--------------------------------------------------------------------+
void board_init(void) {
SCB_EnableICache();
SCB_EnableDCache();
HAL_Init();
board_clock_init();
// Enable All GPIOs clocks

View File

@@ -98,6 +98,11 @@ static void trace_etm_init(void) {
#endif
void board_init(void) {
SCB_EnableICache();
SCB_EnableDCache();
HAL_Init();
// Implemented in board.h
SystemClock_Config();

View File

@@ -124,9 +124,13 @@ void log_swo_init(void)
#endif
void board_init(void) {
SCB_EnableICache();
SCB_EnableDCache();
HAL_Init();
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
// Implemented in board.h
SystemClock_Config();