Check IN ep count limit.
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@@ -103,6 +103,9 @@ static uint16_t ep0_pending[2]; // Index determines direction as t
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// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
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// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
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static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
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static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
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// Number of IN endpoints active
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static uint8_t _allocated_ep_in_count;
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// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
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// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
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static bool _sof_en;
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static bool _sof_en;
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@@ -170,6 +173,12 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
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dwc2->grxfsiz = sz;
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dwc2->grxfsiz = sz;
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}
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}
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} else {
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} else {
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// Check IN endpoints concurrently active limit
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if(_dwc2_controller->ep_in_count) {
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TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count);
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_allocated_ep_in_count++;
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}
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// Note if The TXFELVL is configured as half empty. In order
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// Note if The TXFELVL is configured as half empty. In order
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// to be able to write a packet at that point, the fifo must be twice the max_size.
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// to be able to write a packet at that point, the fifo must be twice the max_size.
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if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
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if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
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@@ -303,6 +312,8 @@ static void bus_reset(uint8_t rhport) {
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_sof_en = false;
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_sof_en = false;
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_allocated_ep_in_count = 1;
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// clear device address
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// clear device address
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dwc2->dcfg &= ~DCFG_DAD_Msk;
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dwc2->dcfg &= ~DCFG_DAD_Msk;
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@@ -770,6 +781,8 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
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uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
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_allocated_ep_in_count = 1;
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// Disable non-control interrupt
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// Disable non-control interrupt
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dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
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dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
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@@ -37,11 +37,12 @@
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//#include "soc/usb_periph.h"
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//#include "soc/usb_periph.h"
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#define DWC2_REG_BASE 0x60080000UL
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#define DWC2_REG_BASE 0x60080000UL
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#define DWC2_EP_MAX 6 // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
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#define DWC2_EP_MAX 7
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#define DWC2_EP_IN_MAX 5
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static const dwc2_controller_t _dwc2_controller[] =
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static const dwc2_controller_t _dwc2_controller[] =
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{
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{
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{ .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
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{ .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_in_count = DWC2_EP_IN_MAX, .ep_fifo_size = 1024 }
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};
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};
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static intr_handle_t usb_ih;
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static intr_handle_t usb_ih;
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@@ -29,6 +29,7 @@ typedef struct
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uintptr_t reg_base;
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uintptr_t reg_base;
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uint32_t irqnum;
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uint32_t irqnum;
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uint8_t ep_count;
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uint8_t ep_count;
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uint8_t ep_in_count;
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uint32_t ep_fifo_size;
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uint32_t ep_fifo_size;
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}dwc2_controller_t;
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}dwc2_controller_t;
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