mass rename TUSB_CFG to CFG_TUSB
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@@ -38,7 +38,7 @@
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#include "common/tusb_common.h"
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#if MODE_HOST_SUPPORTED && (TUSB_CFG_MCU == MCU_LPC43XX || TUSB_CFG_MCU == MCU_LPC18XX)
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#if MODE_HOST_SUPPORTED && (CFG_TUSB_MCU == MCU_LPC43XX || CFG_TUSB_MCU == MCU_LPC18XX)
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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@@ -57,20 +57,20 @@
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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TUSB_CFG_ATTR_USBRAM STATIC_VAR ehci_data_t ehci_data;
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CFG_TUSB_ATTR_USBRAM STATIC_VAR ehci_data_t ehci_data;
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#if EHCI_PERIODIC_LIST
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#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST)
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TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list0[EHCI_FRAMELIST_SIZE];
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#if (CFG_TUSB_CONTROLLER_0_MODE & TUSB_MODE_HOST)
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CFG_TUSB_ATTR_USBRAM ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list0[EHCI_FRAMELIST_SIZE];
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#ifndef __ICCARM__ // IAR cannot able to determine the alignment with datalignment pragma
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VERIFY_STATIC( ALIGN_OF(period_frame_list0) == 4096, "Period Framelist must be 4k alginment"); // validation
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#endif
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#endif
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#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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TUSB_CFG_ATTR_USBRAM ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list1[EHCI_FRAMELIST_SIZE];
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#if (CFG_TUSB_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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CFG_TUSB_ATTR_USBRAM ATTR_ALIGNED(4096) STATIC_VAR ehci_link_t period_frame_list1[EHCI_FRAMELIST_SIZE];
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#ifndef __ICCARM__ // IAR cannot able to determine the alignment with datalignment pragma
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VERIFY_STATIC( ALIGN_OF(period_frame_list1) == 4096, "Period Framelist must be 4k alginment"); // validation
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@@ -133,11 +133,11 @@ tusb_error_t hcd_init(void)
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//------------- Data Structure init -------------//
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memclr_(&ehci_data, sizeof(ehci_data_t));
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#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST)
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#if (CFG_TUSB_CONTROLLER_0_MODE & TUSB_MODE_HOST)
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ASSERT_ERR (hcd_controller_init(0));
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#endif
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#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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#if (CFG_TUSB_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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ASSERT_ERR (hcd_controller_init(1));
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#endif
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@@ -511,7 +511,7 @@ static void async_advance_isr(ehci_qhd_t * const async_head)
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usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
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}
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for(uint8_t relative_dev_addr=0; relative_dev_addr < TUSB_CFG_HOST_DEVICE_MAX; relative_dev_addr++)
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for(uint8_t relative_dev_addr=0; relative_dev_addr < CFG_TUSB_HOST_DEVICE_MAX; relative_dev_addr++)
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{
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// check if control endpoint is removing
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ehci_qhd_t *p_control_qhd = &ehci_data.device[relative_dev_addr].control.qhd;
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@@ -592,7 +592,7 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
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}
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p_qhd = qhd_next(p_qhd);
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max_loop++;
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}while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*TUSB_CFG_HOST_DEVICE_MAX); // async list traversal, stop if loop around
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}while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX); // async list traversal, stop if loop around
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// TODO abstract max loop guard for async
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}
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@@ -606,7 +606,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
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// TODO abstract max loop guard for period
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while( !next_item.terminate &&
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!(interval_ms > 1 && period_1ms_addr == align32(next_item.address)) &&
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max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*TUSB_CFG_HOST_DEVICE_MAX)
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max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUSB_HOST_DEVICE_MAX)
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{
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switch ( next_item.type )
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{
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@@ -691,7 +691,7 @@ static void xfer_error_isr(uint8_t hostid)
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qhd_xfer_error_isr( p_qhd );
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p_qhd = qhd_next(p_qhd);
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max_loop++;
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}while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*TUSB_CFG_HOST_DEVICE_MAX); // async list traversal, stop if loop around
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}while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX); // async list traversal, stop if loop around
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#if EHCI_PERIODIC_LIST
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//------------- TODO refractor period list -------------//
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@@ -704,7 +704,7 @@ static void xfer_error_isr(uint8_t hostid)
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// TODO abstract max loop guard for period
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while( !next_item.terminate &&
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!(interval_ms > 1 && period_1ms_addr == align32(next_item.address)) &&
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period_max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*TUSB_CFG_HOST_DEVICE_MAX)
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period_max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUSB_HOST_DEVICE_MAX)
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{
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switch ( next_item.type )
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{
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@@ -794,12 +794,12 @@ static inline ehci_link_t* get_period_frame_list(uint8_t hostid)
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{
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switch(hostid)
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{
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#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_HOST)
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#if (CFG_TUSB_CONTROLLER_0_MODE & TUSB_MODE_HOST)
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case 0:
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return period_frame_list0;
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#endif
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#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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#if (CFG_TUSB_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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case 1:
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return period_frame_list1;
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#endif
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@@ -811,7 +811,7 @@ static inline ehci_link_t* get_period_frame_list(uint8_t hostid)
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static inline uint8_t hostid_to_data_idx(uint8_t hostid)
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{
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#if (CONTROLLER_HOST_NUMBER == 1) && (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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#if (CONTROLLER_HOST_NUMBER == 1) && (CFG_TUSB_CONTROLLER_1_MODE & TUSB_MODE_HOST)
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(void) hostid;
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return 0;
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#else
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@@ -471,7 +471,7 @@ typedef struct {
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ehci_qtd_t qtd[HCD_MAX_XFER] ATTR_ALIGNED(32) ; ///< Queue Element Transfer Pool
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// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
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// ehci_sitd_t sitd[EHCI_MAX_SITD] ; ///< Split (FS) Isochronous Transfer Pool
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}device[TUSB_CFG_HOST_DEVICE_MAX];
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}device[CFG_TUSB_HOST_DEVICE_MAX];
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}ehci_data_t;
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#ifdef __cplusplus
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