From 3eb04518796e81e41ff119dc5acf33bf5241fdec Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 7 Jul 2025 12:33:14 +0700 Subject: [PATCH] change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1 use stock iar linker --- hw/bsp/stm32h7rs/family.cmake | 2 +- hw/bsp/stm32h7rs/family.mk | 2 +- hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf | 55 ------------------- src/common/tusb_mcu.h | 30 +++++----- src/portable/synopsys/dwc2/dwc2_stm32.h | 10 ++-- src/tusb_option.h | 4 +- 6 files changed, 23 insertions(+), 80 deletions(-) delete mode 100644 hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake index 6b7915c93..40230ef12 100644 --- a/hw/bsp/stm32h7rs/family.cmake +++ b/hw/bsp/stm32h7rs/family.cmake @@ -58,7 +58,7 @@ function(add_board_target BOARD_TARGET) endif() set(LD_FILE_Clang ${LD_FILE_GNU}) if(NOT DEFINED LD_FILE_IAR) - set(LD_FILE_IAR ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.icf) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) endif() add_library(${BOARD_TARGET} STATIC diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk index 45d4da0cf..fba38448d 100644 --- a/hw/bsp/stm32h7rs/family.mk +++ b/hw/bsp/stm32h7rs/family.mk @@ -92,4 +92,4 @@ SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s # Linker LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld -LD_FILE_IAR ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.icf +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf b/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf deleted file mode 100644 index 786be3560..000000000 --- a/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf +++ /dev/null @@ -1,55 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol NONCACHEABLEBUFFER_size = 0x400; -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; -define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; -define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; - - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_ITCM_start__ = 0x00000000; -define symbol __region_ITCM_end__ = 0x0000FFFF; -define symbol __region_DTCM_start__ = 0x20000000; -define symbol __region_DTCM_end__ = 0x2000FFFF; -define symbol __region_SRAMAHB_start__ = 0x30000000; -define symbol __region_SRAMAHB_end__ = 0x30007FFF; -define symbol __region_BKPSRAM_start__ = 0x38800000; -define symbol __region_BKPSRAM_end__ = 0x38800FFF; - -export symbol NONCACHEABLEBUFFER_start; -export symbol NONCACHEABLEBUFFER_size; - -export symbol __ICFEDIT_region_ROM_start__; -export symbol __ICFEDIT_region_ROM_end__; -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; -define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; -define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; -define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; -define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place in DTCM_region { block CSTACK, block HEAP }; -place in NONCACHEABLE_region { section noncacheable_buffer }; diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 4205239f1..94eeb1294 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -117,9 +117,9 @@ #define TUP_RHPORT_HIGHSPEED 1 #if __CORTEX_M == 7 - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #endif #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) @@ -221,9 +221,9 @@ #endif // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #elif TU_CHECK_MCU(OPT_MCU_STM32H7) #include "stm32h7xx.h" @@ -233,10 +233,10 @@ #define TUP_DCD_ENDPOINT_MAX 9 #if __CORTEX_M == 7 - // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + // Enable dcache if DMA is enabled + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #endif #elif TU_CHECK_MCU(OPT_MCU_STM32H5) @@ -336,9 +336,9 @@ #define TUP_RHPORT_HIGHSPEED 1 // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 //--------------------------------------------------------------------+ // Sony @@ -410,8 +410,8 @@ #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64 #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index f9aa5301b..5f2b8419c 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -282,8 +282,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { //------------- DCache -------------// #if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE -typedef struct -{ +typedef struct { uintptr_t start; uintptr_t end; } mem_region_t; @@ -310,16 +309,15 @@ static mem_region_t uncached_regions[] = { }; TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { - if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) { - size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE; + if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) { + size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT; } return size; } TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) { for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) { - if (addr >= uncached_regions[i].start && addr <= uncached_regions[i].end) - return false; + if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; } } return true; } diff --git a/src/tusb_option.h b/src/tusb_option.h index 867babc33..e6f5004b6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -420,7 +420,7 @@ #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 1 #endif #define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT @@ -428,7 +428,7 @@ // OS selection #ifndef CFG_TUSB_OS - #define CFG_TUSB_OS OPT_OS_NONE + #define CFG_TUSB_OS OPT_OS_NONE #endif #ifndef CFG_TUSB_OS_INC_PATH