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move core init code to dwc2 common. update/correct build for esppressif

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This commit is contained in:
hathach
2024-10-15 17:55:24 +07:00
parent 10a3aa3cc8
commit 4012e15075
42 changed files with 172 additions and 141 deletions
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34
src/portable/synopsys/dwc2/dcd_dwc2.c
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@@ -480,21 +480,28 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rh_init;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
TU_ASSERT(dwc2_controller_init(rhport, rh_init));
TU_ASSERT(dwc2_core_init(rhport, rh_init));
// Device Initialization
dcd_disconnect(rhport);
// Restart PHY clock
dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
// Set device max speed
uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
if (dwc2_core_is_highspeed(dwc2, rh_init)) {
dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
/* Set HS/FS Timeout Calibration to 7 (max available value).
* The number of PHY clocks that the application programs in
* this field is added to the high/full speed interpacket timeout
* duration in the core to account for any additional delays
* introduced by the PHY. This can be required, because the delay
* introduced by the PHY in generating the linestate condition
* can vary from one PHY to another.
*/
dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
dcfg |= DCFG_XCVRDLY;
}
}else {
dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos;
}
dwc2->dcfg = dcfg;
// Enable PHY clock TODO stop/gate clock when suspended mode
dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE);
// Force device mode
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
@@ -502,8 +509,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// Clear A override, force B Valid
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
// If USB host misbehaves during status portion of control xfer
// (non zero-length packet), send STALL back and discard.
// If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard
dwc2->dcfg |= DCFG_NZLSOHSK;
dfifo_flush_tx(dwc2, 0x10); // all tx fifo

65
src/portable/synopsys/dwc2/dwc2_common.c
View File

@@ -30,7 +30,14 @@
#if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
#include "common/tusb_common.h"
#if CFG_TUD_ENABLED
#include "device/dcd.h"
#endif
#if CFG_TUH_ENABLED
#include "host/hcd.h"
#endif
#include "dwc2_common.h"
static void reset_core(dwc2_regs_t* dwc2) {
@@ -47,18 +54,24 @@ static void reset_core(dwc2_regs_t* dwc2) {
// wait for device mode ?
}
static bool phy_hs_supported(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
(void) dwc2;
#if !TUD_OPT_HIGH_SPEED
return false;
#else
return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
#if CFG_TUD_ENABLED
if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
return false;
}
#endif
#if CFG_TUH_ENABLED
if (rh_init->role == TUSB_ROLE_DEVICE && !TUH_OPT_HIGH_SPEED) {
return false;
}
#endif
return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
}
static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
static void phy_fs_init(dwc2_regs_t* dwc2) {
TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
// Select FS PHY
@@ -77,12 +90,9 @@ static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
// MCU specific PHY update post reset
dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// set max speed
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
}
static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
static void phy_hs_init(dwc2_regs_t* dwc2) {
uint32_t gusbcfg = dwc2->gusbcfg;
// De-select FS PHY
@@ -137,19 +147,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
// MCU specific PHY update post reset
dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
// Set max speed
uint32_t dcfg = dwc2->dcfg;
dcfg &= ~DCFG_DSPD_Msk;
dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
dcfg |= DCFG_XCVRDLY;
}
dwc2->dcfg = dcfg;
}
static bool check_dwc2(dwc2_regs_t* dwc2) {
@@ -177,19 +174,29 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
//--------------------------------------------------------------------
//
//--------------------------------------------------------------------
bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rh_init;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// Check Synopsys ID register, failed if controller clock/power is not enabled
TU_ASSERT(check_dwc2(dwc2));
if (phy_hs_supported(dwc2, rh_init)) {
phy_hs_init(dwc2, rh_init); // Highspeed
if (dwc2_core_is_highspeed(dwc2, rh_init)) {
phy_hs_init(dwc2); // Highspeed
} else {
phy_fs_init(dwc2, rh_init); // core does not support highspeed or hs phy is not present
phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
}
/* Set HS/FS Timeout Calibration to 7 (max available value).
* The number of PHY clocks that the application programs in
* this field is added to the high/full speed interpacket timeout
* duration in the core to account for any additional delays
* introduced by the PHY. This can be required, because the delay
* introduced by the PHY in generating the linestate condition
* can vary from one PHY to another.
*/
dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
return true;
}

5
src/portable/synopsys/dwc2/dwc2_common.h
View File

@@ -27,6 +27,7 @@
#ifndef TUSB_DWC2_COMMON_H
#define TUSB_DWC2_COMMON_H
#include "common/tusb_common.h"
#include "dwc2_type.h"
// Following symbols must be defined by port header
@@ -64,7 +65,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
}
bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init);
bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
#endif

5
src/portable/synopsys/dwc2/dwc2_esp32.h
View File

@@ -25,13 +25,14 @@
*/
#ifndef _DWC2_ESP32_H_
#define _DWC2_ESP32_H_
#ifndef TUSB_DWC2_ESP32_H_
#define TUSB_DWC2_ESP32_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_intr_alloc.h"

60
src/portable/synopsys/dwc2/dwc2_type.h
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@@ -464,8 +464,8 @@ typedef struct {
uint32_t reservedd00[64]; // D00..DFF
//------------- Power Clock -------------//
volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
volatile uint32_t pcgctl1; // E04
volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control
volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1
uint32_t reservede08[126]; // E08..FFF
//------------- FIFOs -------------//
@@ -478,7 +478,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size");
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size");
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size");
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size");
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgcctl) == 0x0E00, "incorrect size");
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
//--------------------------------------------------------------------+
@@ -720,7 +720,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
/******************** Bit definition for GUSBCFG register ********************/
#define GUSBCFG_TOCAL_Pos (0U)
#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007
#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration
#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // HS/FS timeout calibration
#define GUSBCFG_PHYIF16_Pos (3U)
#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008
#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf)
@@ -1973,32 +1973,32 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000
/******************** Bit definition for PCGCTL register ********************/
#define PCGCTL_IF_DEV_MODE TU_BIT(31)
#define PCGCTL_P2HD_PRT_SPD_MASK (0x3ul << 29)
#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27)
#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
#define PCGCTL_MAC_DEV_ADDR_MASK (0x7ful << 20)
#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
#define PCGCTL_MAX_TERMSEL TU_BIT(19)
#define PCGCTL_MAX_XCVRSELECT_MASK (0x3ul << 17)
#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
#define PCGCTL_PORT_POWER TU_BIT(16)
#define PCGCTL_PRT_CLK_SEL_MASK (0x3ul << 14)
#define PCGCTL_PRT_CLK_SEL_SHIFT 14
#define PCGCTL_ESS_REG_RESTORED TU_BIT(13)
#define PCGCTL_EXTND_HIBER_SWITCH TU_BIT(12)
#define PCGCTL_EXTND_HIBER_PWRCLMP TU_BIT(11)
#define PCGCTL_ENBL_EXTND_HIBER TU_BIT(10)
#define PCGCTL_RESTOREMODE TU_BIT(9)
#define PCGCTL_RESETAFTSUSP TU_BIT(8)
#define PCGCTL_DEEP_SLEEP TU_BIT(7)
#define PCGCTL_PHY_IN_SLEEP TU_BIT(6)
#define PCGCTL_ENBL_SLEEP_GATING TU_BIT(5)
#define PCGCTL_RSTPDWNMODULE TU_BIT(3)
#define PCGCTL_PWRCLMP TU_BIT(2)
#define PCGCTL_GATEHCLK TU_BIT(1)
#define PCGCTL_STOPPCLK TU_BIT(0)
#define PCGCCTL_IF_DEV_MODE TU_BIT(31)
#define PCGCCTL_P2HD_PRT_SPD_MASK (0x3ul << 29)
#define PCGCCTL_P2HD_PRT_SPD_SHIFT 29
#define PCGCCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27)
#define PCGCCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
#define PCGCCTL_MAC_DEV_ADDR_MASK (0x7ful << 20)
#define PCGCCTL_MAC_DEV_ADDR_SHIFT 20
#define PCGCCTL_MAX_TERMSEL TU_BIT(19)
#define PCGCCTL_MAX_XCVRSELECT_MASK (0x3ul << 17)
#define PCGCCTL_MAX_XCVRSELECT_SHIFT 17
#define PCGCCTL_PORT_POWER TU_BIT(16)
#define PCGCCTL_PRT_CLK_SEL_MASK (0x3ul << 14)
#define PCGCCTL_PRT_CLK_SEL_SHIFT 14
#define PCGCCTL_ESS_REG_RESTORED TU_BIT(13)
#define PCGCCTL_EXTND_HIBER_SWITCH TU_BIT(12)
#define PCGCCTL_EXTND_HIBER_PWRCLMP TU_BIT(11)
#define PCGCCTL_ENBL_EXTND_HIBER TU_BIT(10)
#define PCGCCTL_RESTOREMODE TU_BIT(9)
#define PCGCCTL_RESETAFTSUSP TU_BIT(8)
#define PCGCCTL_DEEP_SLEEP TU_BIT(7)
#define PCGCCTL_PHY_IN_SLEEP TU_BIT(6)
#define PCGCCTL_ENBL_SLEEP_GATING TU_BIT(5)
#define PCGCCTL_RSTPDWNMODULE TU_BIT(3)
#define PCGCCTL_PWRCLMP TU_BIT(2)
#define PCGCCTL_GATEHCLK TU_BIT(1)
#define PCGCCTL_STOPPCLK TU_BIT(0)
#define PCGCTL1_TIMER (0x3ul << 1)
#define PCGCTL1_GATEEN TU_BIT(0)