Format doc.
This commit is contained in:
@@ -145,8 +145,7 @@ TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligne
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//--------------------------------------------------------------------+
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// One of these for every EP IN & OUT, uses a bit of RAM....
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typedef struct
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{
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typedef struct {
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uint8_t *buffer;
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tu_fifo_t *ff;
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uint16_t total_len;
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@@ -157,8 +156,7 @@ typedef struct
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} xfer_ctl_t;
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// EP allocator
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typedef struct
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{
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typedef struct {
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uint8_t ep_num;
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uint8_t ep_type;
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bool allocated[2];
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@@ -196,7 +194,8 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
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// Inline helper
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//--------------------------------------------------------------------+
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TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) {
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TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint32_t ep_addr)
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{
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uint8_t epnum = tu_edpt_number(ep_addr);
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uint8_t dir = tu_edpt_dir(ep_addr);
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// Fix -Werror=null-dereference
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@@ -243,8 +242,7 @@ void dcd_init (uint8_t rhport)
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USB->ISTR = 0; // Clear pending interrupts
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// Reset endpoints to disabled
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for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
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{
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for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
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// This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
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pcd_set_endpoint(USB, i, 0u);
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}
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@@ -253,7 +251,8 @@ void dcd_init (uint8_t rhport)
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dcd_handle_bus_reset();
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// Enable pull-up if supported
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if ( dcd_connect ) dcd_connect(rhport);
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if (dcd_connect)
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dcd_connect(rhport);
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}
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// Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
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@@ -294,12 +293,9 @@ void dcd_sof_enable(uint8_t rhport, bool en)
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(void)rhport;
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(void)en;
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if (en)
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{
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if (en) {
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USB->CNTR |= USB_CNTR_SOFM;
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}
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else
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{
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} else {
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USB->CNTR &= ~USB_CNTR_SOFM;
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}
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}
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@@ -311,8 +307,7 @@ void dcd_int_enable (uint8_t rhport)
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// Member here forces write to RAM before allowing ISR to execute
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__DSB();
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__ISB();
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#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
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CFG_TUSB_MCU == OPT_MCU_STM32L4
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#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || CFG_TUSB_MCU == OPT_MCU_STM32L4
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NVIC_EnableIRQ(USB_IRQn);
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#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
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@@ -323,13 +318,11 @@ void dcd_int_enable (uint8_t rhport)
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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#ifdef SYSCFG_CFGR1_USB_IT_RMP
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if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP)
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{
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if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
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NVIC_EnableIRQ(USB_HP_IRQn);
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NVIC_EnableIRQ(USB_LP_IRQn);
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NVIC_EnableIRQ(USBWakeUp_RMP_IRQn);
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}
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else
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} else
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#endif
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{
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NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
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@@ -373,8 +366,7 @@ void dcd_int_disable(uint8_t rhport)
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{
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(void)rhport;
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#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
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CFG_TUSB_MCU == OPT_MCU_STM32L4
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#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || CFG_TUSB_MCU == OPT_MCU_STM32L4
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NVIC_DisableIRQ(USB_IRQn);
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#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
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NVIC_DisableIRQ(USB_LP_IRQn);
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@@ -383,13 +375,11 @@ void dcd_int_disable(uint8_t rhport)
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to disable the right IRQs.
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#ifdef SYSCFG_CFGR1_USB_IT_RMP
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if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP)
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{
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if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
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NVIC_DisableIRQ(USB_HP_IRQn);
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NVIC_DisableIRQ(USB_LP_IRQn);
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NVIC_DisableIRQ(USBWakeUp_RMP_IRQn);
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}
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else
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} else
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#endif
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{
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NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
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@@ -451,35 +441,28 @@ void dcd_remote_wakeup(uint8_t rhport)
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remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
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}
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static const tusb_desc_endpoint_t ep0OUT_desc =
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{
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.bLength = sizeof(tusb_desc_endpoint_t),
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static const tusb_desc_endpoint_t ep0OUT_desc = {.bLength = sizeof(tusb_desc_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x00,
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.bmAttributes = {.xfer = TUSB_XFER_CONTROL},
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.wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
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.bInterval = 0
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};
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.bInterval = 0};
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static const tusb_desc_endpoint_t ep0IN_desc =
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{
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.bLength = sizeof(tusb_desc_endpoint_t),
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static const tusb_desc_endpoint_t ep0IN_desc = {.bLength = sizeof(tusb_desc_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x80,
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.bmAttributes = {.xfer = TUSB_XFER_CONTROL},
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.wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
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.bInterval = 0
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};
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.bInterval = 0};
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static void dcd_handle_bus_reset(void)
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{
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//__IO uint16_t * const epreg = &(EPREG(0));
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USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
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for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
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{
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for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
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// Clear all EPREG (or maybe this is automatic? I'm not sure)
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pcd_set_endpoint(USB, i, 0u);
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@@ -510,8 +493,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
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// Verify the CTR_TX bit is set. This was in the ST Micro code,
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// but I'm not sure it's actually necessary?
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if((wEPRegVal & USB_EP_CTR_TX) == 0U)
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{
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if ((wEPRegVal & USB_EP_CTR_TX) == 0U) {
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return;
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}
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@@ -521,7 +503,8 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
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xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
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/* Ignore spurious int */
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if(xfer->in_complete) return;
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if (xfer->in_complete)
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return;
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xfer->in_complete = true;
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if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
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@@ -535,8 +518,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
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if ((xfer->total_len != xfer->queued_len)) /* TX not complete */
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{
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dcd_transmit_packet(xfer, EPindex);
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}
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else /* TX Complete */
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} else /* TX Complete */
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{
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dcd_event_xfer_complete(0, ep_addr, xfer->total_len, XFER_RESULT_SUCCESS, true);
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}
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@@ -544,7 +526,8 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
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// Handle CTR interrupt for the RX/OUT direction
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// Upon call, (wIstr & USB_ISTR_DIR) == 0U
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static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
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static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
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{
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#ifdef FSDEV_BUS_32BIT
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/* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
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* From STM32H503 errata 2.15.1: Buffer description table update completes after CTR interrupt triggers
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@@ -597,9 +580,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
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dcd_event_setup_received(0, (uint8_t *)userMemBuf, true);
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#endif
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}
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}
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else
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{
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} else {
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// Clear RX CTR interrupt flag
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if (ep_addr != 0u) {
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pcd_clear_rx_ep_ctr(USB, EPindex);
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@@ -623,29 +604,22 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
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TU_ASSERT(count <= xfer->max_packet_size, /**/);
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if (count != 0U)
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{
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if (xfer->ff)
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{
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if (count != 0U) {
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if (xfer->ff) {
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dcd_read_packet_memory_ff(xfer->ff, addr, count);
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}
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else
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{
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} else {
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dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), addr, count);
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}
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
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{
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if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
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/* RX COMPLETE */
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dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
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// Though the host could still send, we don't know.
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// Does the bulk pipe need to be reset to valid to allow for a ZLP?
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}
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else
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{
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} else {
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/* Set endpoint active again for receiving more data.
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* Note that isochronous endpoints stay active always */
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if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
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@@ -661,15 +635,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
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// For EP0, prepare to receive another SETUP packet.
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// Clear CTR last so that a new packet does not overwrite the packing being read.
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// (Based on the docs, it seems SETUP will always be accepted after CTR is cleared)
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if(ep_addr == 0u)
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{
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if (ep_addr == 0u) {
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// Always be prepared for a status packet...
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pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
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pcd_clear_rx_ep_ctr(USB, EPindex);
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}
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}
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static void dcd_ep_ctr_handler(void) {
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static void dcd_ep_ctr_handler(void)
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{
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uint32_t wIstr;
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/* stay in loop while pending interrupts */
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@@ -684,7 +658,8 @@ static void dcd_ep_ctr_handler(void) {
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}
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}
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void dcd_int_handler(uint8_t rhport) {
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void dcd_int_handler(uint8_t rhport)
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{
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(void)rhport;
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@@ -711,15 +686,13 @@ void dcd_int_handler(uint8_t rhport) {
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return; // Don't do the rest of the things here; perhaps they've been cleared?
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}
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if (int_status & USB_ISTR_CTR)
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{
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if (int_status & USB_ISTR_CTR) {
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/* servicing of the endpoint correct transfer interrupt */
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/* clear of the CTR flag into the sub */
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dcd_ep_ctr_handler();
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}
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if (int_status & USB_ISTR_WKUP)
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{
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if (int_status & USB_ISTR_WKUP) {
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USB->CNTR &= ~USB_CNTR_LPMODE;
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USB->CNTR &= ~USB_CNTR_FSUSP;
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@@ -727,8 +700,7 @@ void dcd_int_handler(uint8_t rhport) {
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dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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}
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if (int_status & USB_ISTR_SUSP)
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{
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if (int_status & USB_ISTR_SUSP) {
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/* Suspend is asserted for both suspend and unplug events. without Vbus monitoring,
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* these events cannot be differentiated, so we only trigger suspend. */
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@@ -742,12 +714,10 @@ void dcd_int_handler(uint8_t rhport) {
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}
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if (int_status & USB_ISTR_ESOF) {
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if(remoteWakeCountdown == 1u)
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{
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if (remoteWakeCountdown == 1u) {
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USB->CNTR &= ~USB_CNTR_RESUME;
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}
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if(remoteWakeCountdown > 0u)
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{
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if (remoteWakeCountdown > 0u) {
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remoteWakeCountdown--;
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}
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USB->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
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@@ -764,10 +734,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
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{
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(void)rhport;
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if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
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request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
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request->bRequest == TUSB_REQ_SET_ADDRESS )
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{
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if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS) {
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uint8_t const dev_addr = (uint8_t)request->wValue;
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// Setting new address after the whole request is complete
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@@ -812,29 +779,19 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
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{
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for (uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) {
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// Check if already allocated
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if(ep_alloc_status[i].allocated[dir] &&
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ep_alloc_status[i].ep_type == ep_type &&
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ep_alloc_status[i].ep_num == epnum)
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{
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if (ep_alloc_status[i].allocated[dir] && ep_alloc_status[i].ep_type == ep_type && ep_alloc_status[i].ep_num == epnum) {
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return i;
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}
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// If EP of current direction is not allocated
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// Except for ISO endpoint, both direction should be free
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if(!ep_alloc_status[i].allocated[dir] &&
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(ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1]))
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{
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if (!ep_alloc_status[i].allocated[dir] && (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) {
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// Check if EP number is the same
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if(ep_alloc_status[i].ep_num == 0xFF ||
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ep_alloc_status[i].ep_num == epnum)
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{
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if (ep_alloc_status[i].ep_num == 0xFF || ep_alloc_status[i].ep_num == epnum) {
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// One EP pair has to be the same type
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if(ep_alloc_status[i].ep_type == 0xFF ||
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ep_alloc_status[i].ep_type == ep_type)
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{
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if (ep_alloc_status[i].ep_type == 0xFF || ep_alloc_status[i].ep_type == ep_type) {
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ep_alloc_status[i].ep_num = epnum;
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ep_alloc_status[i].ep_type = ep_type;
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ep_alloc_status[i].allocated[dir] = true;
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@@ -891,15 +848,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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/* Create a packet memory buffer area. */
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pma_addr = dcd_pma_alloc(buffer_size, false);
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if(dir == TUSB_DIR_IN)
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{
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if (dir == TUSB_DIR_IN) {
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pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
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pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
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pcd_clear_tx_dtog(USB, ep_idx);
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}
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if(dir == TUSB_DIR_OUT)
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{
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if (dir == TUSB_DIR_OUT) {
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pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
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pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
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pcd_clear_rx_dtog(USB, ep_idx);
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@@ -932,12 +887,9 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
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uint8_t const ep_idx = xfer->ep_idx;
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uint8_t const dir = tu_edpt_dir(ep_addr);
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if(dir == TUSB_DIR_IN)
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{
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if (dir == TUSB_DIR_IN) {
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pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
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}
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else
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{
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} else {
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pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
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}
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}
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@@ -1023,12 +975,9 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
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pcd_set_ep_tx_cnt(USB, ep_ix, len);
|
||||
}
|
||||
|
||||
if (xfer->ff)
|
||||
{
|
||||
if (xfer->ff) {
|
||||
dcd_write_packet_memory_ff(xfer->ff, addr_ptr, len);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dcd_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len);
|
||||
}
|
||||
xfer->queued_len = (uint16_t)(xfer->queued_len + len);
|
||||
@@ -1047,12 +996,10 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
|
||||
uint8_t const ep_idx = xfer->ep_idx;
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
if ( dir == TUSB_DIR_OUT )
|
||||
{
|
||||
if (dir == TUSB_DIR_OUT) {
|
||||
// A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
|
||||
// buffer for the control endpoint.
|
||||
if (ep_idx == 0 && xfer->buffer == NULL)
|
||||
{
|
||||
if (ep_idx == 0 && xfer->buffer == NULL) {
|
||||
xfer->buffer = (uint8_t *)_setup_packet;
|
||||
}
|
||||
|
||||
@@ -1067,8 +1014,7 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
|
||||
}
|
||||
|
||||
pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
|
||||
}
|
||||
else // IN
|
||||
} else // IN
|
||||
{
|
||||
dcd_transmit_packet(xfer, ep_idx);
|
||||
}
|
||||
@@ -1106,12 +1052,9 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
uint8_t const ep_idx = xfer->ep_idx;
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
if (dir == TUSB_DIR_IN)
|
||||
{ // IN
|
||||
if (dir == TUSB_DIR_IN) { // IN
|
||||
pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_STALL);
|
||||
}
|
||||
else
|
||||
{ // OUT
|
||||
} else { // OUT
|
||||
pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_STALL);
|
||||
}
|
||||
}
|
||||
@@ -1124,17 +1067,14 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
uint8_t const ep_idx = xfer->ep_idx;
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
if (dir == TUSB_DIR_IN)
|
||||
{ // IN
|
||||
if (dir == TUSB_DIR_IN) { // IN
|
||||
if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) {
|
||||
pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
|
||||
}
|
||||
|
||||
/* Reset to DATA0 if clearing stall condition. */
|
||||
pcd_clear_tx_dtog(USB, ep_idx);
|
||||
}
|
||||
else
|
||||
{ // OUT
|
||||
} else { // OUT
|
||||
if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) {
|
||||
pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
|
||||
}
|
||||
@@ -1155,18 +1095,15 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
|
||||
}
|
||||
|
||||
wNBytes = wNBytes & 0x03;
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
uint32_t wrVal = *srcVal;
|
||||
wNBytes--;
|
||||
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
wrVal |= *++srcVal << 8;
|
||||
wNBytes--;
|
||||
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
wrVal |= *++srcVal << 16;
|
||||
}
|
||||
}
|
||||
@@ -1201,8 +1138,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
|
||||
srcVal = src;
|
||||
pdwVal = &pma[FSDEV_PMA_STRIDE * (dst >> 1)];
|
||||
|
||||
while (n--)
|
||||
{
|
||||
while (n--) {
|
||||
temp1 = (uint16_t)*srcVal;
|
||||
srcVal++;
|
||||
temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U));
|
||||
@@ -1211,8 +1147,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
|
||||
srcVal++;
|
||||
}
|
||||
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
temp1 = *srcVal;
|
||||
*pdwVal = temp1;
|
||||
}
|
||||
@@ -1240,8 +1175,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
|
||||
// last lin byte will be combined with wrapped part
|
||||
// To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
|
||||
#ifdef FSDEV_BUS_32BIT
|
||||
if((cnt_lin & 0x03) && cnt_wrap)
|
||||
{
|
||||
if ((cnt_lin & 0x03) && cnt_wrap) {
|
||||
// Copy first linear part
|
||||
dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin & ~0x03);
|
||||
dst += cnt_lin & ~0x03;
|
||||
@@ -1249,13 +1183,11 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
|
||||
// Copy last linear bytes & first wrapped bytes to buffer
|
||||
uint32_t i;
|
||||
uint8_t tmp[4];
|
||||
for (i = 0; i < (cnt_lin & 0x03); i++)
|
||||
{
|
||||
for (i = 0; i < (cnt_lin & 0x03); i++) {
|
||||
tmp[i] = ((uint8_t *)info.ptr_lin)[(cnt_lin & ~0x03) + i];
|
||||
}
|
||||
uint32_t wCnt = cnt_wrap;
|
||||
for (; i < 4 && wCnt > 0; i++, wCnt--)
|
||||
{
|
||||
for (; i < 4 && wCnt > 0; i++, wCnt--) {
|
||||
tmp[i] = *(uint8_t *)info.ptr_wrap;
|
||||
info.ptr_wrap = (uint8_t *)info.ptr_wrap + 1;
|
||||
}
|
||||
@@ -1269,8 +1201,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
|
||||
dcd_write_packet_memory(dst, info.ptr_wrap, wCnt);
|
||||
}
|
||||
#else
|
||||
if((cnt_lin & 0x01) && cnt_wrap)
|
||||
{
|
||||
if ((cnt_lin & 0x01) && cnt_wrap) {
|
||||
// Copy first linear part
|
||||
dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin & ~0x01);
|
||||
dst += cnt_lin & ~0x01;
|
||||
@@ -1284,14 +1215,12 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
|
||||
dcd_write_packet_memory(dst, ((uint8_t *)info.ptr_wrap) + 1, cnt_wrap - 1);
|
||||
}
|
||||
#endif
|
||||
else
|
||||
{
|
||||
else {
|
||||
// Copy linear part
|
||||
dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin);
|
||||
dst += info.len_lin;
|
||||
|
||||
if(info.len_wrap)
|
||||
{
|
||||
if (info.len_wrap) {
|
||||
// Copy wrapped byte
|
||||
dcd_write_packet_memory(dst, info.ptr_wrap, cnt_wrap);
|
||||
}
|
||||
@@ -1314,20 +1243,17 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
|
||||
}
|
||||
|
||||
wNBytes = wNBytes & 0x03;
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
uint32_t rdVal = *src32;
|
||||
|
||||
*dstVal = tu_u32_byte0(rdVal);
|
||||
wNBytes--;
|
||||
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
*++dstVal = tu_u32_byte1(rdVal);
|
||||
wNBytes--;
|
||||
|
||||
if (wNBytes)
|
||||
{
|
||||
if (wNBytes) {
|
||||
*++dstVal = tu_u32_byte2(rdVal);
|
||||
}
|
||||
}
|
||||
@@ -1353,16 +1279,14 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
|
||||
pdwVal = &pma[FSDEV_PMA_STRIDE * (src >> 1)];
|
||||
uint8_t *dstVal = (uint8_t *)dst;
|
||||
|
||||
while (n--)
|
||||
{
|
||||
while (n--) {
|
||||
temp = *pdwVal;
|
||||
pdwVal += FSDEV_PMA_STRIDE;
|
||||
*dstVal++ = ((temp >> 0) & 0xFF);
|
||||
*dstVal++ = ((temp >> 8) & 0xFF);
|
||||
}
|
||||
|
||||
if (wNBytes & 0x01)
|
||||
{
|
||||
if (wNBytes & 0x01) {
|
||||
temp = *pdwVal;
|
||||
pdwVal += FSDEV_PMA_STRIDE;
|
||||
*dstVal++ = ((temp >> 0) & 0xFF);
|
||||
@@ -1387,13 +1311,11 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
|
||||
uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin);
|
||||
uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
|
||||
|
||||
|
||||
// We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
|
||||
// last lin byte will be combined with wrapped part
|
||||
// To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
|
||||
#ifdef FSDEV_BUS_32BIT
|
||||
if((cnt_lin & 0x03) && cnt_wrap)
|
||||
{
|
||||
if ((cnt_lin & 0x03) && cnt_wrap) {
|
||||
// Copy first linear part
|
||||
dcd_read_packet_memory(info.ptr_lin, src, cnt_lin & ~0x03);
|
||||
src += cnt_lin & ~0x03;
|
||||
@@ -1404,13 +1326,11 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
|
||||
src += 4;
|
||||
|
||||
uint32_t i;
|
||||
for (i = 0; i < (cnt_lin & 0x03); i++)
|
||||
{
|
||||
for (i = 0; i < (cnt_lin & 0x03); i++) {
|
||||
((uint8_t *)info.ptr_lin)[(cnt_lin & ~0x03) + i] = tmp[i];
|
||||
}
|
||||
uint32_t wCnt = cnt_wrap;
|
||||
for (; i < 4 && wCnt > 0; i++, wCnt--)
|
||||
{
|
||||
for (; i < 4 && wCnt > 0; i++, wCnt--) {
|
||||
*(uint8_t *)info.ptr_wrap = tmp[i];
|
||||
info.ptr_wrap = (uint8_t *)info.ptr_wrap + 1;
|
||||
}
|
||||
@@ -1420,8 +1340,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
|
||||
dcd_read_packet_memory(info.ptr_wrap, src, wCnt);
|
||||
}
|
||||
#else
|
||||
if((cnt_lin & 0x01) && cnt_wrap)
|
||||
{
|
||||
if ((cnt_lin & 0x01) && cnt_wrap) {
|
||||
// Copy first linear part
|
||||
dcd_read_packet_memory(info.ptr_lin, src, cnt_lin & ~0x01);
|
||||
src += cnt_lin & ~0x01;
|
||||
@@ -1438,14 +1357,12 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
|
||||
dcd_read_packet_memory(((uint8_t *)info.ptr_wrap) + 1, src, cnt_wrap - 1);
|
||||
}
|
||||
#endif
|
||||
else
|
||||
{
|
||||
else {
|
||||
// Copy linear part
|
||||
dcd_read_packet_memory(info.ptr_lin, src, cnt_lin);
|
||||
src += cnt_lin;
|
||||
|
||||
if(info.len_wrap)
|
||||
{
|
||||
if (info.len_wrap) {
|
||||
// Copy wrapped byte
|
||||
dcd_read_packet_memory(info.ptr_wrap, src, cnt_wrap);
|
||||
}
|
||||
|
Reference in New Issue
Block a user