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Use PLL clock.

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This commit is contained in:
HiFiPhile
2023-04-14 17:12:47 +02:00
parent 0ea23904c4
commit 413b0a7da5
3 changed files with 21 additions and 32 deletions
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38
hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
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@@ -62,7 +62,7 @@ static inline void board_clock_init(void)
{ {
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_CRSInitTypeDef pInit = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
/** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now /** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now
*/ */
@@ -75,38 +75,32 @@ static inline void board_clock_init(void)
/** Initializes the RCC Oscillators according to the specified parameters /** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure. * in the RCC_OscInitTypeDef structure.
*/ */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.PLL.PLLN = 12;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
HAL_RCC_OscConfig(&RCC_OscInitStruct); HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select HSI48 as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/** Initializes the CPU, AHB and APB buses clocks /** Initializes the CPU, AHB and APB buses clocks
*/ */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1; |RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
/** Enable the SYSCFG APB clock
*/
__HAL_RCC_CRS_CLK_ENABLE();
/** Configures CRS
*/
pInit.Prescaler = RCC_CRS_SYNC_DIV1;
pInit.Source = RCC_CRS_SYNC_SOURCE_USB;
pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
pInit.ErrorLimitValue = 34;
pInit.HSI48CalibrationValue = 32;
HAL_RCCEx_CRSConfig(&pInit);
} }
#ifdef __cplusplus #ifdef __cplusplus

12
hw/bsp/stm32g0/family.c
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@@ -53,6 +53,9 @@ void board_init(void)
__HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE();
UART_CLK_EN(); UART_CLK_EN();
#if CFG_TUSB_OS == OPT_OS_NONE #if CFG_TUSB_OS == OPT_OS_NONE
@@ -119,16 +122,7 @@ void board_init(void)
__HAL_RCC_USB_CLK_ENABLE(); __HAL_RCC_USB_CLK_ENABLE();
/* Enable VDDUSB */ /* Enable VDDUSB */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSB(); HAL_PWREx_EnableVddUSB();
__HAL_RCC_PWR_CLK_DISABLE();
}
else
{
HAL_PWREx_EnableVddUSB();
}
} }
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+

1
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
View File

@@ -44,6 +44,7 @@
* L0x2, L0x3 1024 byte buffer * L0x2, L0x3 1024 byte buffer
* L1 512 byte buffer * L1 512 byte buffer
* L4x2, L4x3 1024 byte buffer * L4x2, L4x3 1024 byte buffer
* G0 2048 byte buffer
* *
* To use this driver, you must: * To use this driver, you must:
* - If you are using a device with crystal-less USB, set up the clock recovery system (CRS) * - If you are using a device with crystal-less USB, set up the clock recovery system (CRS)