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Merge remote-tracking branch 'upstream/master' into edpt_ISO_xfer

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This commit is contained in:
Reinhard Panhuber
2021-01-09 12:10:08 +01:00
parent 09d8ead4b8 cfcffe94ce
commit 485d8fa77e
23 changed files with 867 additions and 124 deletions
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2
src/class/hid/hid_device.h
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@@ -46,7 +46,7 @@
#endif
#ifndef CFG_TUD_HID_EP_BUFSIZE
#define CFG_TUD_HID_EP_BUFSIZE 16
#define CFG_TUD_HID_EP_BUFSIZE 64
#endif
//--------------------------------------------------------------------+

18
src/device/usbd.c
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@@ -1103,6 +1103,24 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
{
TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, desc_ep->wMaxPacketSize.size);
if (TUSB_XFER_ISOCHRONOUS == desc_ep->bmAttributes.xfer)
{
TU_ASSERT(desc_ep->wMaxPacketSize.size <= (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 1023));
}
else
{
uint16_t const max_epsize = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 512 : 64);
if (TUSB_XFER_BULK == desc_ep->bmAttributes.xfer)
{
// Bulk must be EXACTLY 512/64 bytes
TU_ASSERT(desc_ep->wMaxPacketSize.size == max_epsize);
}else
{
TU_ASSERT(desc_ep->wMaxPacketSize.size <= max_epsize);
}
}
return dcd_edpt_open(rhport, desc_ep);
}

7
src/portable/dialog/da146xx/dcd_da146xx.c
View File

@@ -664,7 +664,7 @@ static void handle_bus_reset(void)
(void)USB->USB_ALTEV_REG;
_dcd.in_reset = true;
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
USB->USB_DMA_CTRL_REG = 0;
USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
@@ -821,14 +821,13 @@ void dcd_disconnect(uint8_t rhport)
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
{
(void)rhport;
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
uint8_t iso_mask = 0;
(void)rhport;
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 1023);
TU_ASSERT(epnum < EP_MAX);
xfer->max_packet_size = desc_edpt->wMaxPacketSize.size;

1
src/portable/espressif/esp32s2/dcd_esp32s2.c
View File

@@ -252,7 +252,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
TU_ASSERT(epnum < EP_MAX);
xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);

15
src/portable/microchip/samd/dcd_samd.c
View File

@@ -37,14 +37,23 @@
/* MACRO TYPEDEF CONSTANT ENUM
*------------------------------------------------------------------*/
static TU_ATTR_ALIGNED(4) UsbDeviceDescBank sram_registers[8][2];
static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8];
// Setup packet is only 8 bytes in length. However under certain scenario,
// USB DMA controller may decide to overwrite/overflow the buffer with
// 2 extra bytes of CRC. From datasheet's "Management of SETUP Transactions" section
// If the number of received data bytes is the maximum data payload specified by
// PCKSIZE.SIZE minus one, only the first CRC data is written to the data buffer.
// If the number of received data is equal or less than the data payload specified
// by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
// Therefore we will need to increase it to 10 bytes here.
static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8+2];
// ready for receiving SETUP packet
static inline void prepare_setup(void)
{
// Only make sure the EP0 OUT buffer is ready
sram_registers[0][0].ADDR.reg = (uint32_t) _setup_packet;
sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(_setup_packet);
sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(tusb_control_request_t);
sram_registers[0][0].PCKSIZE.bit.BYTE_COUNT = 0;
}
@@ -378,7 +387,7 @@ void dcd_int_handler (uint8_t rhport)
USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_SUSPEND;
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
}
// Handle SETUP packet

2
src/portable/microchip/samg/dcd_samg.c
View File

@@ -338,7 +338,7 @@ void dcd_int_handler(uint8_t rhport)
if (intr_status & UDP_ISR_ENDBUSRES_Msk)
{
bus_reset();
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
}
// SOF

2
src/portable/nordic/nrf5x/dcd_nrf5x.c
View File

@@ -533,7 +533,7 @@ void dcd_int_handler(uint8_t rhport)
if ( int_status & USBD_INTEN_USBRESET_Msk )
{
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
}
// ISOIN: Data was moved to endpoint buffer, client will be notified in SOF

3
src/portable/nuvoton/nuc120/dcd_nuc120.c
View File

@@ -329,8 +329,7 @@ void dcd_int_handler(uint8_t rhport)
USBD->ATTR |= USBD_ATTR_USB_EN_Msk | USBD_ATTR_PHY_EN_Msk;
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
}
if(state & USBD_STATE_SUSPEND)

2
src/portable/nuvoton/nuc121/dcd_nuc121.c
View File

@@ -340,7 +340,7 @@ void dcd_int_handler(uint8_t rhport)
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
}
if(state & USBD_ATTR_SUSPEND_Msk)

2
src/portable/nxp/khci/dcd_khci.c
View File

@@ -224,7 +224,7 @@ static void process_bus_reset(uint8_t rhport)
_dcd.addr = 0;
prepare_next_setup_packet(rhport);
KHCI->CTL &= ~USB_CTL_ODDRST_MASK;
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
}
static void process_bus_inactive(uint8_t rhport)

2
src/portable/nxp/lpc17_40/dcd_lpc17_40.c
View File

@@ -471,7 +471,7 @@ static void bus_event_isr(uint8_t rhport)
if (dev_status & SIE_DEV_STATUS_RESET_MASK)
{
bus_reset();
dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
}
if (dev_status & SIE_DEV_STATUS_CONNECT_CHANGE_MASK)

4
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
View File

@@ -243,7 +243,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
(void) rhport;
// TODO not support ISO yet
if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
TU_VERIFY(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
//------------- Prepare Queue Head -------------//
uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
@@ -357,7 +357,7 @@ void dcd_int_handler(uint8_t rhport)
if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
{
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
}
if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)

2
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
View File

@@ -547,7 +547,7 @@ void dcd_int_handler(uint8_t rhport) {
// USBRST is start of reset.
clear_istr_bits(USB_ISTR_RESET);
dcd_handle_bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
return; // Don't do the rest of the things here; perhaps they've been cleared?
}

215
src/portable/st/synopsys/dcd_synopsys.c
View File

@@ -46,13 +46,13 @@
#define STM32L4_SYNOPSYS
#endif
#if TUSB_OPT_DEVICE_ENABLED && \
#if TUSB_OPT_DEVICE_ENABLED && \
( (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
CFG_TUSB_MCU == OPT_MCU_STM32F2 || \
CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
CFG_TUSB_MCU == OPT_MCU_STM32F2 || \
CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
)
// EP_MAX : Max number of bi-directional endpoints including EP0
@@ -116,6 +116,7 @@
#define EP_FIFO_SIZE EP_FIFO_SIZE_HS
#define RHPORT_REGS_BASE USB_OTG_HS_PERIPH_BASE
#define RHPORT_IRQn OTG_HS_IRQn
#endif
#define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
@@ -141,25 +142,40 @@ typedef struct {
uint8_t interval;
} xfer_ctl_t;
// EP size and transfer type report
typedef struct TU_ATTR_PACKED {
// The following format may look complicated but it is the most elegant way of addressing the required fields: EP number, EP direction, and EP transfer type.
// The codes assigned to those fields, according to the USB specification, can be neatly used as indices.
uint16_t ep_size[EP_MAX][2]; ///< dim 1: EP number, dim 2: EP direction denoted by TUSB_DIR_OUT (= 0) and TUSB_DIR_IN (= 1)
bool ep_transfer_type[EP_MAX][2][4]; ///< dim 1: EP number, dim 2: EP direction, dim 3: transfer type, where 0 = Control, 1 = Isochronous, 2 = Bulk, and 3 = Interrupt
///< I know very well that EP0 can only be used as control EP and we waste space here but for the sake of simplicity we accept that. It is used in a non-persistent way anyway!
} ep_sz_tt_report_t;
typedef volatile uint32_t * usb_fifo_t;
xfer_ctl_t xfer_status[EP_MAX][2];
#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
// EP0 transfers are limited to 1 packet - larger sizes has to be split
static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
// FIFO RAM allocation so far in words
static uint16_t _allocated_fifo_words;
// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size)
// Calculate the RX FIFO size according to recommendations from reference manual
static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
{
return 15 + 2*(ep_size/4) + 2*EP_MAX;
}
static void update_grxfsiz(uint8_t rhport)
{
(void) rhport;
USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
// Determine largest EP size for RX FIFO
uint16_t max_epsize = 0;
for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
{
max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
}
// Update size of RX FIFO
usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
}
// Setup the control endpoint 0.
static void bus_reset(uint8_t rhport)
@@ -172,6 +188,7 @@ static void bus_reset(uint8_t rhport)
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
tu_memclr(xfer_status, sizeof(xfer_status));
_out_ep_closed = false;
for(uint8_t n = 0; n < EP_MAX; n++) {
out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
@@ -184,16 +201,28 @@ static void bus_reset(uint8_t rhport)
// "USB Data FIFOs" section in reference manual
// Peripheral FIFO architecture
//
// The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
// We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
// between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
// configuration done below.
//
// Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
// All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
// configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
// opened when the host sends an additional command: setInterface. At this point in time
// the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
// an additional memory
//
// --------------- 320 or 1024 ( 1280 or 4096 bytes )
// | IN FIFO 0 |
// --------------- (320 or 1024) - 16
// | IN FIFO 1 |
// --------------- (320 or 1024) - 16 - x
// | . . . . |
// --------------- (320 or 1024) - 16 - x - y - ... - z
// | IN FIFO MAX |
// ---------------
// | ... |
// --------------- y + x + 16 + GRXFSIZ
// | IN FIFO 2 |
// --------------- x + 16 + GRXFSIZ
// | IN FIFO 1 |
// --------------- 16 + GRXFSIZ
// | IN FIFO 0 |
// | FREE |
// --------------- GRXFSIZ
// | OUT FIFO |
// | ( Shared ) |
@@ -215,24 +244,16 @@ static void bus_reset(uint8_t rhport)
// NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
// of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
//
// FIXME: for Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
// For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
// are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
// overwrite this.
#if TUD_OPT_HIGH_SPEED
_allocated_fifo_words = 271 + 2*EP_MAX;
#else
_allocated_fifo_words = 47 + 2*EP_MAX;
#endif
usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
usb_otg->GRXFSIZ = _allocated_fifo_words;
_allocated_fifo_words_tx = 16;
// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | _allocated_fifo_words;
_allocated_fifo_words += 16;
// TU_LOG2_INT(_allocated_fifo_words);
usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
// Fixed control EP0 size to 64 bytes
in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
@@ -536,6 +557,8 @@ void dcd_disconnect(uint8_t rhport)
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
{
(void) rhport;
USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
@@ -546,21 +569,26 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
TU_ASSERT(epnum < EP_MAX);
if (desc_edpt->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
{
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 1024 : 1023));
}
else
{
TU_ASSERT(desc_edpt->wMaxPacketSize.size <= (get_speed(rhport) == TUSB_SPEED_HIGH ? 512 : 64));
}
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
xfer->max_size = desc_edpt->wMaxPacketSize.size;
xfer->interval = desc_edpt->bInterval;
uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word
if(dir == TUSB_DIR_OUT)
{
// Calculate required size of RX FIFO
uint16_t const sz = calc_rx_ff_size(4*fifo_size);
// If size_rx needs to be extended check if possible and if so enlarge it
if (usb_otg->GRXFSIZ < sz)
{
TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
// Enlarge RX FIFO
usb_otg->GRXFSIZ = sz;
}
out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
(desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
(desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
@@ -573,15 +601,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
// Peripheral FIFO architecture
//
// --------------- 320 or 1024 ( 1280 or 4096 bytes )
// | IN FIFO 0 |
// --------------- (320 or 1024) - 16
// | IN FIFO 1 |
// --------------- (320 or 1024) - 16 - x
// | . . . . |
// --------------- (320 or 1024) - 16 - x - y - ... - z
// | IN FIFO MAX |
// ---------------
// | ... |
// --------------- y + x + 16 + GRXFSIZ
// | IN FIFO 2 |
// --------------- x + 16 + GRXFSIZ
// | IN FIFO 1 |
// --------------- 16 + GRXFSIZ
// | IN FIFO 0 |
// | FREE |
// --------------- GRXFSIZ
// | OUT FIFO |
// | ( Shared ) |
@@ -589,34 +617,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
//
// In FIFO is allocated by following rules:
// - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
// - Offset: allocated so far
// - Size
// - Interrupt is EPSize
// - Bulk/ISO is max(EPSize, remaining-fifo / non-opened-EPIN)
uint16_t const fifo_remaining = EP_FIFO_SIZE/4 - _allocated_fifo_words;
uint16_t fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // +3 for rounding up to next full word
// Check if free space is available
TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
if ( desc_edpt->bmAttributes.xfer != TUSB_XFER_INTERRUPT )
{
uint8_t opened = 0;
for(uint8_t i = 0; i < EP_MAX; i++)
{
if ( (i != epnum) && (xfer_status[i][TUSB_DIR_IN].max_size > 0) ) opened++;
}
// EP Size or equally divided of remaining whichever is larger
fifo_size = tu_max16(fifo_size, fifo_remaining / (EP_MAX - opened));
}
// FIFO overflows, we probably need a better allocating scheme
TU_ASSERT(fifo_size <= fifo_remaining);
_allocated_fifo_words_tx += fifo_size;
// DIEPTXF starts at FIFO #1.
// Both TXFD and TXSA are in unit of 32-bit words.
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | _allocated_fifo_words;
_allocated_fifo_words += fifo_size;
usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
(epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
@@ -758,13 +767,21 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
uint8_t const dir = tu_edpt_dir(ep_addr);
dcd_edpt_disable(rhport, ep_addr, false);
// Update max_size
xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation
if (dir == TUSB_DIR_IN)
{
uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
// For now only endpoint that has FIFO at the end of FIFO memory can be closed without fuss.
TU_ASSERT(fifo_start + fifo_size == _allocated_fifo_words,);
_allocated_fifo_words -= fifo_size;
// For now only the last opened endpoint can be closed without fuss.
TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
_allocated_fifo_words_tx -= fifo_size;
}
else
{
_out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
}
}
@@ -1025,13 +1042,15 @@ void dcd_int_handler(uint8_t rhport)
uint32_t int_status = usb_otg->GINTSTS;
if(int_status & USB_OTG_GINTSTS_USBRST) {
if(int_status & USB_OTG_GINTSTS_USBRST)
{
// USBRST is start of reset.
usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
bus_reset(rhport);
}
if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
if(int_status & USB_OTG_GINTSTS_ENUMDNE)
{
// ENUMDNE is the end of reset where speed of the link is detected
usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
@@ -1068,45 +1087,59 @@ void dcd_int_handler(uint8_t rhport)
}
#if USE_SOF
if(int_status & USB_OTG_GINTSTS_SOF) {
if(int_status & USB_OTG_GINTSTS_SOF)
{
usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
}
#endif
// RxFIFO non-empty interrupt handling.
if(int_status & USB_OTG_GINTSTS_RXFLVL) {
if(int_status & USB_OTG_GINTSTS_RXFLVL)
{
// RXFLVL bit is read-only
// Mask out RXFLVL while reading data from FIFO
usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
// Loop until all available packets were handled
do {
do
{
handle_rxflvl_ints(rhport, out_ep);
int_status = usb_otg->GINTSTS;
} while(int_status & USB_OTG_GINTSTS_RXFLVL);
// Manage RX FIFO size
if (_out_ep_closed)
{
update_grxfsiz(rhport);
// Disable flag
_out_ep_closed = false;
}
usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
}
// OUT endpoint interrupt handling.
if(int_status & USB_OTG_GINTSTS_OEPINT) {
if(int_status & USB_OTG_GINTSTS_OEPINT)
{
// OEPINT is read-only
handle_epout_ints(rhport, dev, out_ep);
}
// IN endpoint interrupt handling.
if(int_status & USB_OTG_GINTSTS_IEPINT) {
if(int_status & USB_OTG_GINTSTS_IEPINT)
{
// IEPINT bit read-only
handle_epin_ints(rhport, dev, in_ep);
}
// // Check for Incomplete isochronous IN transfer
// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
// printf(" IISOIXFR!\r\n");
//// TU_LOG2(" IISOIXFR!\r\n");
// }
// // Check for Incomplete isochronous IN transfer
// if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
// printf(" IISOIXFR!\r\n");
//// TU_LOG2(" IISOIXFR!\r\n");
// }
}
#endif

6
src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
View File

@@ -232,9 +232,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
// Unsupported endpoint numbers/size or type (Iso not supported. Control
// Unsupported endpoint numbers or type (Iso not supported. Control
// not supported on nonzero endpoints).
if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 7) || \
if( (epnum > 7) || \
(desc_edpt->bmAttributes.xfer == 0) || \
(desc_edpt->bmAttributes.xfer == 1)) {
return false;
@@ -572,7 +572,7 @@ void dcd_int_handler(uint8_t rhport)
{
case USBVECINT_RSTR:
bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
break;
// Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet

2
src/portable/valentyusb/eptri/dcd_eptri.c
View File

@@ -332,7 +332,7 @@ static void dcd_reset(void)
usb_out_ev_enable_write(1);
usb_setup_ev_enable_write(3);
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
}
// Initializes the USB peripheral for device mode and enables it.

12
src/tusb_option.h
View File

@@ -151,22 +151,22 @@
#define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
#endif
#if ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST ) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST )) || \
((CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE))
#if (((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST ) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST )) || \
(((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE))
#error "TinyUSB currently does not support same modes on more than 1 roothub port"
#endif
// Which roothub port is configured as host
#define TUH_OPT_RHPORT ( (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) ? 1 : -1) )
#define TUH_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
#define TUSB_OPT_HOST_ENABLED ( TUH_OPT_RHPORT >= 0 )
// Which roothub port is configured as device
#define TUD_OPT_RHPORT ( (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) ? 1 : -1) )
#define TUD_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
#if TUD_OPT_RHPORT == 0
#define TUD_OPT_HIGH_SPEED ( CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED )
#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
#else
#define TUD_OPT_HIGH_SPEED ( CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED )
#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
#endif
#define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 )