- update ch203 family to allow to specify flash and ram size. Introduce

- add ch32v203_ro_1v0 board
- CFG_EXAMPLE_MSC_DUAL_READONLY to build msc_dual_lun for ch32v203

hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.cmake

@@ -0,0 +1,10 @@
+set(MCU_VARIANT D6)
+
+set(LD_FLASH_SIZE 64K)
+set(LD_RAM_SIZE 20K)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_DUAL_READONLY
+    )
+endfunction()

hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.h

@@ -0,0 +1,17 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT       GPIOA
+#define LED_PIN        GPIO_Pin_15
+#define LED_STATE_ON   0
+#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

hw/bsp/ch32v20x/boards/ch32v203_r0_1v0/board.mk

@@ -0,0 +1,7 @@
+MCU_VARIANT = D6
+
+CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
+
+LDFLAGS += \
+  -Wl,--defsym=__flash_size=64K \
+  -Wl,--defsym=__ram_size=20K \

hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake

@@ -1,7 +1,10 @@
 set(MCU_VARIANT D6)
 
+set(LD_FLASH_SIZE 64K)
+set(LD_RAM_SIZE 20K)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
-    CH32V20x_D6
+    CFG_EXAMPLE_MSC_DUAL_READONLY
     )
 endfunction()

hw/bsp/ch32v20x/boards/nanoch32v203/board.mk

@@ -1,5 +1,7 @@
-CFLAGS += \
-	-DCH32V20x_D6
+MCU_VARIANT = D6
 
-SRC_S += \
-	$(CH32V20X_SDK_SRC)/Startup/startup_ch32v20x_D6.S
+CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
+
+LDFLAGS += \
+  -Wl,--defsym=__flash_size=64K \
+  -Wl,--defsym=__ram_size=20K \

hw/bsp/ch32v20x/family.cmake

@@ -1,7 +1,8 @@
 include_guard()
 
 set(CH32_FAMILY ch32v20x)
-set(SDK_DIR ${TOP}/hw/mcu/wch/${CH32_FAMILY}/EVT/EXAM/SRC)
+set(SDK_DIR ${TOP}/hw/mcu/wch/${CH32_FAMILY})
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
 
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
@@ -23,29 +24,30 @@ function(add_board_target BOARD_TARGET)
   endif()
 
   if (NOT DEFINED LD_FILE_GNU)
-    set(LD_FILE_GNU ${SDK_DIR}/Ld/Link.ld)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${CH32_FAMILY}.ld)
   endif ()
   set(LD_FILE_Clang ${LD_FILE_GNU})
 
   if (NOT DEFINED STARTUP_FILE_GNU)
-    set(STARTUP_FILE_GNU ${SDK_DIR}/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S)
+    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S)
   endif ()
   set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
   add_library(${BOARD_TARGET} STATIC
-    ${SDK_DIR}/Core/core_riscv.c
-    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
-    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
-    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
-    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
-    ${SDK_DIR}/Peripheral/inc
+    ${SDK_SRC_DIR}/Peripheral/inc
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CH32V20x_${MCU_VARIANT}
     BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
     )
 
@@ -57,6 +59,8 @@ function(add_board_target BOARD_TARGET)
       )
     target_link_options(${BOARD_TARGET} PUBLIC
       "LINKER:--script=${LD_FILE_GNU}"
+      -Wl,--defsym=__flash_size=${LD_FLASH_SIZE}
+      -Wl,--defsym=__ram_size=${LD_RAM_SIZE}
       -nostartfiles
       --specs=nosys.specs --specs=nano.specs
       )

hw/bsp/ch32v20x/family.mk

@@ -7,12 +7,9 @@
 # Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
 CROSS_COMPILE ?= riscv-none-elf-
 
-# Submodules
-CH32V20X_SDK = hw/mcu/wch/ch32v20x
-DEPS_SUBMODULES += $(CH32V20X_SDK)
-
-# WCH-SDK paths
-CH32V20X_SDK_SRC = $(CH32V20X_SDK)/EVT/EXAM/SRC
+CH32_FAMILY = ch32v20x
+SDK_DIR = hw/mcu/wch/ch32v20x
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= rv32imac-ilp32
@@ -23,27 +20,29 @@ CFLAGS += \
 	-fdata-sections \
 	-ffat-lto-objects \
 	-flto \
+	-DCH32V20x_${MCU_VARIANT} \
 	-DCFG_TUSB_MCU=OPT_MCU_CH32V20X \
 	-DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \
 
 LDFLAGS_GCC += \
-	-Wl,--gc-sections \
 	-nostdlib -nostartfiles \
 	--specs=nosys.specs --specs=nano.specs \
 
-LD_FILE = $(CH32V20X_SDK_SRC)/Ld/Link.ld
+LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
 
 SRC_C += \
 	src/portable/wch/dcd_ch32_usbfs.c \
-	$(CH32V20X_SDK_SRC)/Core/core_riscv.c \
-	$(CH32V20X_SDK_SRC)/Peripheral/src/ch32v20x_gpio.c \
-	$(CH32V20X_SDK_SRC)/Peripheral/src/ch32v20x_misc.c \
-	$(CH32V20X_SDK_SRC)/Peripheral/src/ch32v20x_rcc.c \
-	$(CH32V20X_SDK_SRC)/Peripheral/src/ch32v20x_usart.c \
+	$(SDK_SRC_DIR)/Core/core_riscv.c \
+	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/ch32v20x_usart.c \
+
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_ch32v20x_${MCU_VARIANT}.S
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(CH32V20X_SDK_SRC)/Peripheral/inc \
+	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
 
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 

hw/bsp/ch32v20x/linker/ch32v20x.ld

@@ -0,0 +1 @@
+/* Define default values if not already defined */