add tud_ready() check in tud_cdc_n_write_flush()
other clean up
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@@ -178,6 +178,9 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf)
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{
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cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
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// Skip if usb is not ready yet
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TU_VERIFY( tud_ready(), 0 );
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// No data to send
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if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
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@@ -231,9 +234,10 @@ void cdcd_init(void)
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p_cdc->line_coding.parity = 0;
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p_cdc->line_coding.data_bits = 8;
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// config fifo
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// Config RX fifo
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tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false);
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// tx fifo is set to overwritable at initialization and will be changed to not overwritable
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// Config TX fifo as overwritable at initialization and will be changed to non-overwritable
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// if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal.
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// In this way, the most current data is prioritized.
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tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
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@@ -251,9 +255,12 @@ void cdcd_reset(uint8_t rhport)
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for(uint8_t i=0; i<CFG_TUD_CDC; i++)
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{
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tu_memclr(&_cdcd_itf[i], ITF_MEM_RESET_SIZE);
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tu_fifo_clear(&_cdcd_itf[i].rx_ff);
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tu_fifo_clear(&_cdcd_itf[i].tx_ff);
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cdcd_interface_t* p_cdc = &_cdcd_itf[i];
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tu_memclr(p_cdc, ITF_MEM_RESET_SIZE);
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tu_fifo_clear(&p_cdc->rx_ff);
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tu_fifo_clear(&p_cdc->tx_ff);
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tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
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}
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}
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@@ -381,7 +388,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
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p_cdc->line_state = (uint8_t) request->wValue;
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// Disable fifo overwriting if DTR bit is set
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tu_fifo_set_mode(&p_cdc->tx_ff, !dtr);
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tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
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TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
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