simplify dwc2 test mode
- all dwc2 ip seems to support test mode in both fs/hs -> remove TUP_USBIP_DWC2_TEST_MODE - remove dcd_check_test_mode_support(), all should be supported - move enum tusb_feature_test_mode_t to tusb_types.h
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@@ -195,7 +195,6 @@
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#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
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#define TUP_USBIP_DWC2
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#define TUP_USBIP_DWC2_STM32
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#define TUP_USBIP_DWC2_TEST_MODE
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// For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
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#define TUP_DCD_ENDPOINT_MAX 6
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@@ -210,7 +209,6 @@
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// MCU with on-chip HS Phy
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#if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
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#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
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#define TUP_USBIP_DWC2_TEST_MODE
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#endif
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#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
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@@ -285,7 +283,6 @@
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defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
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#define TUP_DCD_ENDPOINT_MAX 9
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#define TUP_RHPORT_HIGHSPEED 1
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#define TUP_USBIP_DWC2_TEST_MODE
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#else
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#define TUP_DCD_ENDPOINT_MAX 6
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#endif
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