have p4 dma somewhat working but having issue with buffer that does not occupy the whole cache line
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@@ -15,6 +15,13 @@ list(APPEND compile_definitions
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BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
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)
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if (target STREQUAL esp32p4)
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# P4 change alignment to 64 (DCache line size) for possible DMA configuration
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list(APPEND compile_definitions
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CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
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)
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endif ()
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list(APPEND srcs
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# common
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${tusb_src}/tusb.c
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@@ -68,6 +75,7 @@ endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${tusb_src}
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REQUIRES src
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PRIV_REQUIRES esp_mm
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)
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target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
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