have p4 dma somewhat working but having issue with buffer that does not occupy the whole cache line

This commit is contained in:
hathach
2024-11-20 18:03:42 +07:00
parent 43a45f29cd
commit 4da5de707b
6 changed files with 104 additions and 18 deletions

View File

@@ -15,6 +15,13 @@ list(APPEND compile_definitions
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
)
if (target STREQUAL esp32p4)
# P4 change alignment to 64 (DCache line size) for possible DMA configuration
list(APPEND compile_definitions
CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
)
endif ()
list(APPEND srcs
# common
${tusb_src}/tusb.c
@@ -68,6 +75,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${tusb_src}
REQUIRES src
PRIV_REQUIRES esp_mm
)
target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})