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This commit is contained in:
hathach
2021-08-12 00:12:15 +07:00
parent 88d4cb402d
commit 4f2999bc04

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@@ -70,13 +70,13 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
return hw_endpoint_get_by_num(num, dir); return hw_endpoint_get_by_num(num, dir);
} }
static void _hw_endpoint_alloc(struct hw_endpoint *ep) static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
{ {
// size must be multiple of 64 // size must be multiple of 64
uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u; uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
// double buffered for Control and Bulk endpoint // double buffered for Control and Bulk endpoint
if ( ep->transfer_type == TUSB_XFER_CONTROL || ep->transfer_type == TUSB_XFER_BULK) if ( transfer_type == TUSB_XFER_CONTROL || transfer_type == TUSB_XFER_BULK )
{ {
size *= 2u; size *= 2u;
} }
@@ -96,7 +96,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
ep_dir_string[tu_edpt_dir(ep->ep_addr)]); ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
// Fill in endpoint control register with buffer offset // Fill in endpoint control register with buffer offset
uint32_t const reg = EP_CTRL_ENABLE_BITS | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
*ep->endpoint_control = reg; *ep->endpoint_control = reg;
} }
@@ -139,7 +139,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
ep->transfer_type = transfer_type; ep->transfer_type = transfer_type;
// Every endpoint has a buffer control register in dpram // Every endpoint has a buffer control register in dpram
if (dir == TUSB_DIR_IN) if ( dir == TUSB_DIR_IN )
{ {
ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in; ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
} }
@@ -151,33 +151,33 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
// Clear existing buffer control state // Clear existing buffer control state
*ep->buffer_control = 0; *ep->buffer_control = 0;
if (num == 0) if ( num == 0 )
{ {
// EP0 has no endpoint control register because // EP0 has no endpoint control register because
// the buffer offsets are fixed // the buffer offsets are fixed
ep->endpoint_control = NULL; ep->endpoint_control = NULL;
// Buffer offset is fixed // Buffer offset is fixed
ep->hw_data_buf = (uint8_t*)&usb_dpram->ep0_buf_a[0]; ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
} }
else else
{ {
// Set the endpoint control register (starts at EP1, hence num-1) // Set the endpoint control register (starts at EP1, hence num-1)
if (dir == TUSB_DIR_IN) if ( dir == TUSB_DIR_IN )
{ {
ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].in; ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
} }
else else
{ {
ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].out; ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
} }
// Now if it hasn't already been done // Now if it hasn't already been done
// alloc a buffer and fill in endpoint control register // alloc a buffer and fill in endpoint control register
// TODO device may change configuration (dynamic), should clear and reallocate // TODO device may change configuration (dynamic), should clear and reallocate
if(!(ep->configured)) if ( !(ep->configured) )
{ {
_hw_endpoint_alloc(ep); _hw_endpoint_alloc(ep, transfer_type);
} }
} }