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		@@ -70,13 +70,13 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
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  return hw_endpoint_get_by_num(num, dir);
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					  return hw_endpoint_get_by_num(num, dir);
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}
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					}
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static void _hw_endpoint_alloc(struct hw_endpoint *ep)
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					static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
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{
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					{
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  // size must be multiple of 64
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					  // size must be multiple of 64
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  uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
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					  uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
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  // double buffered for Control and Bulk endpoint
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					  // double buffered for Control and Bulk endpoint
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  if ( ep->transfer_type == TUSB_XFER_CONTROL || ep->transfer_type == TUSB_XFER_BULK)
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					  if ( transfer_type == TUSB_XFER_CONTROL || transfer_type == TUSB_XFER_BULK )
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  {
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					  {
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    size *= 2u;
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					    size *= 2u;
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  }
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					  }
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@@ -96,7 +96,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
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            ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
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					            ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
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  // Fill in endpoint control register with buffer offset
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					  // Fill in endpoint control register with buffer offset
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  uint32_t const reg = EP_CTRL_ENABLE_BITS | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
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					  uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
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  *ep->endpoint_control = reg;
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					  *ep->endpoint_control = reg;
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}
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					}
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@@ -122,66 +122,66 @@ static void hw_endpoint_close(uint8_t ep_addr)
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static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
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					static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
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{
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					{
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    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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					  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
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    const uint8_t num = tu_edpt_number(ep_addr);
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					  const uint8_t num = tu_edpt_number(ep_addr);
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    const tusb_dir_t dir = tu_edpt_dir(ep_addr);
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					  const tusb_dir_t dir = tu_edpt_dir(ep_addr);
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    ep->ep_addr = ep_addr;
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					  ep->ep_addr = ep_addr;
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    // For device, IN is a tx transfer and OUT is an rx transfer
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					  // For device, IN is a tx transfer and OUT is an rx transfer
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    ep->rx = (dir == TUSB_DIR_OUT);
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					  ep->rx = (dir == TUSB_DIR_OUT);
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    // Response to a setup packet on EP0 starts with pid of 1
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					  // Response to a setup packet on EP0 starts with pid of 1
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    ep->next_pid = (num == 0 ? 1u : 0u);
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					  ep->next_pid = (num == 0 ? 1u : 0u);
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    ep->wMaxPacketSize = wMaxPacketSize;
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					  ep->wMaxPacketSize = wMaxPacketSize;
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    ep->transfer_type = transfer_type;
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					  ep->transfer_type = transfer_type;
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    // Every endpoint has a buffer control register in dpram
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					  // Every endpoint has a buffer control register in dpram
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    if (dir == TUSB_DIR_IN)
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					  if ( dir == TUSB_DIR_IN )
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					  {
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					    ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
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					  }
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					  else
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					  {
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					    ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
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					  }
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					  // Clear existing buffer control state
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					  *ep->buffer_control = 0;
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					  if ( num == 0 )
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					  {
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					    // EP0 has no endpoint control register because
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					    // the buffer offsets are fixed
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					    ep->endpoint_control = NULL;
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					    // Buffer offset is fixed
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					    ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
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					  }
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					  else
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					  {
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					    // Set the endpoint control register (starts at EP1, hence num-1)
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					    if ( dir == TUSB_DIR_IN )
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    {
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					    {
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        ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
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					      ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
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    }
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					    }
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    else
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					    else
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    {
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					    {
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        ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
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					      ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
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    }
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					    }
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    // Clear existing buffer control state
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					    // Now if it hasn't already been done
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    *ep->buffer_control = 0;
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					    // alloc a buffer and fill in endpoint control register
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					    // TODO device may change configuration (dynamic), should clear and reallocate
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    if (num == 0)
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					    if ( !(ep->configured) )
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    {
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					    {
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        // EP0 has no endpoint control register because
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					      _hw_endpoint_alloc(ep, transfer_type);
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        // the buffer offsets are fixed
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        ep->endpoint_control = NULL;
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        // Buffer offset is fixed
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        ep->hw_data_buf = (uint8_t*)&usb_dpram->ep0_buf_a[0];
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    }
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					    }
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    else
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					  }
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    {
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        // Set the endpoint control register (starts at EP1, hence num-1)
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        if (dir == TUSB_DIR_IN)
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        {
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            ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].in;
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        }
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        else
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        {
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            ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].out;
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        }
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        // Now if it hasn't already been done
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					  ep->configured = true;
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        // alloc a buffer and fill in endpoint control register
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        // TODO device may change configuration (dynamic), should clear and reallocate
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        if(!(ep->configured))
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        {
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            _hw_endpoint_alloc(ep);
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        }
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    }
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    ep->configured = true;
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}
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					}
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static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
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					static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
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