Update build system.
This commit is contained in:
		@@ -42,6 +42,9 @@
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 * See http://www.freertos.org/a00110.html.
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 *----------------------------------------------------------*/
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// skip if included from IAR assembler
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#ifndef __IASMARM__
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// Include MCU header
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#include "bsp/board_mcu.h"
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@@ -53,9 +56,12 @@
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#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
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  extern u32 SystemCoreClock;
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#else
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  // FIXME cause redundant-decls warnings
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  extern uint32_t SystemCoreClock;
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#endif
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#endif
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/* Cortex M23/M33 port configuration. */
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#define configENABLE_MPU								        0
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#define configENABLE_FPU								        1
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@@ -68,14 +74,14 @@
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#define configTICK_RATE_HZ                      ( 1000 )
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#define configMAX_PRIORITIES                    ( 5 )
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#define configMINIMAL_STACK_SIZE                ( 128 )
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#define configTOTAL_HEAP_SIZE                   ( 0*1024 ) // dynamic is not used
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#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
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#define configMAX_TASK_NAME_LEN                 16
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#define configUSE_16_BIT_TICKS                  0
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#define configIDLE_SHOULD_YIELD                 1
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#define configUSE_MUTEXES                       1
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#define configUSE_RECURSIVE_MUTEXES             1
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#define configUSE_COUNTING_SEMAPHORES           1
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#define configQUEUE_REGISTRY_SIZE               2
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#define configQUEUE_REGISTRY_SIZE               4
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#define configUSE_QUEUE_SETS                    0
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#define configUSE_TIME_SLICING                  0
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#define configUSE_NEWLIB_REENTRANT              0
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@@ -90,6 +96,7 @@
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#define configUSE_TICK_HOOK                    0
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#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
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#define configCHECK_FOR_STACK_OVERFLOW         2
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#define configCHECK_HANDLER_INSTALLATION       0
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/* Run time and task stats gathering related definitions. */
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#define configGENERATE_RUN_TIME_STATS          0
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@@ -124,29 +131,12 @@
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#define INCLUDE_xEventGroupSetBitFromISR       0
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#define INCLUDE_xTimerPendFunctionCall         0
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/* Define to trap errors during development. */
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// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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  #define configASSERT(_exp) \
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    do {\
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      if ( !(_exp) ) { \
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        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
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        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
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          taskDISABLE_INTERRUPTS(); \
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           __asm("BKPT #0\n"); \
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        }\
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      }\
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    } while(0)
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#else
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  #define configASSERT( x )
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#endif
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#ifdef __RX__
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/* Renesas RX series */
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#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
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#define vTickISR								INT_Excep_CMT0_CMI0
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#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
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#define configKERNEL_INTERRUPT_PRIORITY			1
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#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
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#define vTickISR								              INT_Excep_CMT0_CMI0
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#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
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#define configKERNEL_INTERRUPT_PRIORITY			  1
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
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#else
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@@ -162,9 +152,18 @@
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#if defined(__NVIC_PRIO_BITS)
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  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
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	#define configPRIO_BITS       __NVIC_PRIO_BITS
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#elif defined(__ECLIC_INTCTLBITS)
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  // RISC-V Bumblebee core from nuclei
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  #define configPRIO_BITS       __ECLIC_INTCTLBITS
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#elif defined(__IASMARM__)
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  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
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  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
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  // IAR user must update this to correct value of the target MCU
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  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
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  #define configPRIO_BITS       2
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#else
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  #error "FreeRTOS configPRIO_BITS to be defined"
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#endif
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