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Merge pull request #3103 from wavenumber-eng/mcxa156__sdk216

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Added initial support for FRDM-MCXA156 and fixed up  a crash with FRDM-MCXN947
This commit is contained in:
Ha Thach
2025-05-16 22:32:04 +07:00
committed by GitHub
parent 3024bff12f d221d55b08
commit 5428b87948
26 changed files with 5156 additions and 101 deletions
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2
hw/bsp/lpc51/family.cmake
View File

@@ -36,7 +36,7 @@ function(add_board_target BOARD_TARGET)
# driver
${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
${SDK_DIR}/drivers/flexcomm/fsl_usart.c
${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c

7
hw/bsp/lpc51/family.mk
View File

@@ -28,15 +28,16 @@ SRC_C += \
$(MCU_DIR)/drivers/fsl_reset.c \
$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
$(TOP)/$(SDK_DIR)/drivers/flexcomm \
$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
$(TOP)/$(SDK_DIR)/drivers/lpc_gpio

3
hw/bsp/lpc54/family.cmake
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@@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET)
${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
${SDK_DIR}/drivers/common/fsl_common_arm.c
${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
${SDK_DIR}/drivers/flexcomm/fsl_usart.c
${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -56,6 +56,7 @@ function(add_board_target BOARD_TARGET)
# driver
${SDK_DIR}/drivers/common
${SDK_DIR}/drivers/flexcomm
${SDK_DIR}/drivers/flexcomm/usart
${SDK_DIR}/drivers/lpc_iocon
${SDK_DIR}/drivers/lpc_gpio
${SDK_DIR}/drivers/lpuart

3
hw/bsp/lpc54/family.mk
View File

@@ -36,7 +36,7 @@ SRC_C += \
$(MCU_DIR)/drivers/fsl_reset.c \
$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
$(SDK_DIR)/drivers/common/fsl_common_arm.c
INC += \
@@ -46,6 +46,7 @@ INC += \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
$(TOP)/$(SDK_DIR)/drivers/flexcomm \
$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
$(TOP)/$(SDK_DIR)/drivers/lpc_gpio

4
hw/bsp/lpc55/family.cmake
View File

@@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET)
${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
${SDK_DIR}/drivers/common/fsl_common_arm.c
${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
${SDK_DIR}/drivers/flexcomm/fsl_usart.c
${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -56,9 +56,9 @@ function(add_board_target BOARD_TARGET)
# driver
${SDK_DIR}/drivers/common
${SDK_DIR}/drivers/flexcomm
${SDK_DIR}/drivers/flexcomm/usart
${SDK_DIR}/drivers/lpc_iocon
${SDK_DIR}/drivers/lpc_gpio
${SDK_DIR}/drivers/lpuart
${SDK_DIR}/drivers/sctimer
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}

7
hw/bsp/lpc55/family.mk
View File

@@ -45,7 +45,7 @@ SRC_C += \
$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
$(SDK_DIR)/drivers/common/fsl_common_arm.c \
$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
$(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \
lib/sct_neopixel/sct_neopixel.c
INC += \
@@ -55,11 +55,10 @@ INC += \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
$(TOP)/$(SDK_DIR)/drivers/flexcomm \
$(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \
$(TOP)/$(SDK_DIR)/drivers/flexcomm/ \
$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
$(TOP)/$(SDK_DIR)/drivers/lpc_gpio \
$(TOP)/$(SDK_DIR)/drivers/sctimer
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a

4
hw/bsp/mcx/boards/frdm_mcxa153/board.h
View File

@@ -39,10 +39,10 @@ extern "C" {
// LED
#define LED_GPIO GPIO3
#define LED_CLK kCLOCK_GateGPIO3
#define LED_PIN 12 // red
#define LED_PIN 12 //red
#define LED_STATE_ON 0
// ISP button (Dummy, use unused pin
// ISP button
#define BUTTON_GPIO GPIO3
#define BUTTON_CLK kCLOCK_GateGPIO3
#define BUTTON_PIN 29 //sw2

4
hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c
View File

@@ -45,14 +45,13 @@ processor_version: 0.13.0
* Variables
******************************************************************************/
/* System clock frequency. */
//uint32_t SystemCoreClock;
//extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockFRO96M();
}
/*******************************************************************************
@@ -386,7 +385,6 @@ void BOARD_BootClockFRO64M(void)
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO96M
called_from_default_init: true
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}

53
hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c
View File

@@ -4,7 +4,6 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
@@ -18,16 +17,13 @@ product: Pins v14.0
processor: MCXA153
package_id: MCXA153VLH
mcu_data: ksdk2_0
processor_version: 0.14.3
pin_labels:
- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
processor_version: 0.14.4
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
@@ -47,8 +43,10 @@ void BOARD_InitBootPins(void)
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
- {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
@@ -61,15 +59,6 @@ BOARD_InitPins:
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
/* write to PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* Write to GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO3);
/* Write to PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT3);
@@ -78,30 +67,13 @@ void BOARD_InitPins(void)
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as P3_12 */
kPORT_MuxAlt0,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT3_12 (pin 38) is configured as P3_12 */
PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
/* Write to PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* LPUART0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
/* PORT0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
@@ -152,7 +124,6 @@ void BOARD_InitPins(void)
kPORT_UnlockRegister};
/* PORT0_3 (pin 52) is configured as LPUART0_TXD */
PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
}
/***********************************************************************************************************************
* EOF

6
hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h
View File

@@ -1,9 +1,13 @@
/*
* Copyright 2022 NXP
* Copyright 2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_

21
hw/bsp/mcx/boards/frdm_mcxa156/board.cmake Normal file
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@@ -0,0 +1,21 @@
set(MCU_VARIANT MCXA156)
set(MCU_CORE MCXA156)
set(JLINK_DEVICE MCXA156_M33)
set(PYOCD_TARGET MCXA156)
set(NXPLINK_DEVICE MCXA156:MCXA156)
set(PORT 0)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CPU_MCXA156VLH
BOARD_TUD_RHPORT=0
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
CFG_EXAMPLE_VIDEO_READONLY
)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
)
endfunction()

69
hw/bsp/mcx/boards/frdm_mcxa156/board.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: Freedom MCXA156
url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// LED
#define LED_GPIO GPIO3
#define LED_CLK kCLOCK_GateGPIO3
#define LED_PIN 12 // red
#define LED_STATE_ON 0
// ISP button
#define BUTTON_GPIO GPIO0
#define BUTTON_CLK kCLOCK_GateGPIO0
#define BUTTON_PIN 6 //SW3
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART0
static inline void board_uart_init_clock(void) {
/* attach 12 MHz clock to LPUART0 (debug console) */
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
}
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
#ifdef __cplusplus
}
#endif
#endif

14
hw/bsp/mcx/boards/frdm_mcxa156/board.mk Normal file
View File

@@ -0,0 +1,14 @@
MCU_VARIANT = MCXA156
MCU_CORE = MCXA156
PORT = 0
CPU_CORE = cortex-m33-nodsp-nofp
CFLAGS += \
-DCPU_MCXA156VLH \
-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
JLINK_DEVICE = MCXA156
PYOCD_TARGET = MCXA156
# flash using pyocd
flash: flash-jlink

482
hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c Normal file
View File

@@ -0,0 +1,482 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to setup clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v13.0
processor: MCXA156
package_id: MCXA156VLL
mcu_data: ksdk2_0
processor_version: 0.15.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_clock.h"
#include "clock_config.h"
#include "fsl_spc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
//extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockFRO96M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CPU_clock.outFreq, value: 12 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: MAIN_clock.outFreq, value: 12 MHz}
- {id: Slow_clock.outFreq, value: 3 MHz}
- {id: System_clock.outFreq, value: 12 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO24M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 24 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 6 MHz}
- {id: System_clock.outFreq, value: 24 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO24M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO24M configuration
******************************************************************************/
void BOARD_BootClockFRO24M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO48M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 48 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
- {id: FRO_HF_clock.outFreq, value: 48 MHz}
- {id: MAIN_clock.outFreq, value: 48 MHz}
- {id: Slow_clock.outFreq, value: 12 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO48M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO48M configuration
******************************************************************************/
void BOARD_BootClockFRO48M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO64M
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 64 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
- {id: FRO_HF_clock.outFreq, value: 64 MHz}
- {id: MAIN_clock.outFreq, value: 64 MHz}
- {id: Slow_clock.outFreq, value: 16 MHz}
- {id: System_clock.outFreq, value: 64 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 64 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO64M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO64M configuration
******************************************************************************/
void BOARD_BootClockFRO64M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO96M
called_from_default_init: true
outputs:
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
- {id: CPU_clock.outFreq, value: 96 MHz}
- {id: FRO_12M_clock.outFreq, value: 12 MHz}
- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
- {id: FRO_HF_clock.outFreq, value: 96 MHz}
- {id: MAIN_clock.outFreq, value: 96 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 96 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
settings:
- {id: VDD_CORE, value: voltage_1v1}
- {id: CLKOUTDIV_HALT, value: Enable}
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
sources:
- {id: SCG.FIRC.outFreq, value: 96 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO96M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO96M configuration
******************************************************************************/
void BOARD_BootClockFRO96M(void)
{
uint32_t coreFreq;
spc_active_mode_core_ldo_option_t ldoOption;
spc_sram_voltage_config_t sramOption;
/* Get the CPU Core frequency */
coreFreq = CLOCK_GetCoreSysClkFreq();
/* The flow of increasing voltage and frequency */
if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
}
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
/* The flow of decreasing voltage and frequency */
if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
/* Configure Flash to support different voltage level and frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
/* Specifies the operating voltage for the SRAM's read/write timing margin */
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
sramOption.requestVoltageUpdate = true;
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
/* Set the LDO_CORE VDD regulator level */
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
}
/*!< Set up clock selectors - Attach clocks to the peripheries */
/*!< Set up dividers */
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
/* Set SystemCoreClock variable */
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
}

169
hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h Normal file
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@@ -0,0 +1,169 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO24M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO24M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO24M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO24M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO48M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO48M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO48M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO48M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO64M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO64M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO64M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO64M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO96M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO96M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO96M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO96M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

144
hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c Normal file
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@@ -0,0 +1,144 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v15.0
processor: MCXA156
package_id: MCXA156VLL
mcu_data: ksdk2_0
processor_version: 0.15.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void)
{
BOARD_InitPins();
}
/* clang-format off */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
- pin_list:
- {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
- {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void)
{
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
CLOCK_AttachClk(kFRO12M_to_LPUART0);
/* GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO3);
/* PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT3);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
/* GPIO3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GateGPIO0);
/* PORT3: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* GPIO3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
/* PORT3 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
/* PORT0: Peripheral clock is enabled */
CLOCK_EnableClock(kCLOCK_GatePORT0);
/* LPUART0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
/* PORT0 peripheral is released from reset */
RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_RXD */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_2 (pin 78) is configured as LPUART0_RXD */
PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config);
const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */
kPORT_PullUp,
/* Low internal pull resistor value is selected. */
kPORT_LowPullResistor,
/* Fast slew rate is configured */
kPORT_FastSlewRate,
/* Passive input filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain output is disabled */
kPORT_OpenDrainDisable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Normal drive strength is configured */
kPORT_NormalDriveStrength,
/* Pin is configured as LPUART0_TXD */
kPORT_MuxAlt2,
/* Digital input enabled */
kPORT_InputBufferEnable,
/* Digital input is not inverted */
kPORT_InputNormal,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORT0_3 (pin 79) is configured as LPUART0_TXD */
PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

51
hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h Normal file
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@@ -0,0 +1,51 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

13
hw/bsp/mcx/boards/frdm_mcxn947/board.h
View File

@@ -49,17 +49,22 @@
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_DEV LPUART4
#define UART_DEV LPUART4
#define LP_FLEXCOMM_INST 4
#include "fsl_lpflexcomm.h"
static inline void board_uart_init_clock(void) {
/* attach FRO 12M to FLEXCOMM4 */
LP_FLEXCOMM_Init(LP_FLEXCOMM_INST, LP_FLEXCOMM_PERIPH_LPUART);
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
}
//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN
//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN
}
// XTAL
#define XTAL0_CLK_HZ (24 * 1000 * 1000U)

1680
hw/bsp/mcx/drivers/spc/fsl_spc.c Normal file
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File diff suppressed because it is too large Load Diff

2433
hw/bsp/mcx/drivers/spc/fsl_spc.h Normal file
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File diff suppressed because it is too large Load Diff

30
hw/bsp/mcx/family.c
View File

@@ -60,9 +60,14 @@ void USB0_IRQHandler(void) {
void board_init(void) {
BOARD_InitPins();
BOARD_InitBootClocks();
#ifdef XTAL0_CLK_HZ
CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
#endif
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
@@ -84,15 +89,7 @@ void board_init(void) {
board_led_write(0);
#ifdef NEOPIXEL_PIN
// Neopixel
static uint32_t pixelData[NEOPIXEL_NUMBER];
IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
sctpix_init(NEOPIXEL_TYPE);
sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
sctpix_show();
// No neo pixel support yet
#endif
// Button
@@ -103,9 +100,6 @@ void board_init(void) {
#endif
#ifdef UART_DEV
// UART
// IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
// IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
// Enable UART when debug log is on
board_uart_init_clock();
@@ -115,6 +109,7 @@ void board_init(void) {
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
uart_config.enableTx = true;
uart_config.enableRx = true;
LPUART_Init(UART_DEV, &uart_config, 12000000u);
#endif
@@ -196,17 +191,6 @@ void board_init(void) {
void board_led_write(bool state) {
GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
#ifdef NEOPIXEL_PIN
if (state) {
sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
} else {
sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
}
sctpix_show();
#endif
}
uint32_t board_button_read(void) {

28
hw/bsp/mcx/family.cmake
View File

@@ -10,6 +10,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
if (MCU_VARIANT STREQUAL "MCXA153")
set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
elseif (MCU_VARIANT STREQUAL "MCXA156")
set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
elseif (MCU_VARIANT STREQUAL "MCXN947")
set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor")
set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
@@ -38,12 +41,14 @@ function(add_board_target BOARD_TARGET)
endif()
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
add_library(${BOARD_TARGET} STATIC
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
# driver
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
${SDK_DIR}/drivers/gpio/fsl_gpio.c
${SDK_DIR}/drivers/common/fsl_common_arm.c
${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c
# mcu
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
@@ -51,18 +56,27 @@ function(add_board_target BOARD_TARGET)
)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMSIS_DIR}/CMSIS/Core/Include
${SDK_DIR}/drivers/gpio/
${SDK_DIR}/drivers/lpuart
${SDK_DIR}/drivers/common
${SDK_DIR}/drivers/port
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc
${SDK_DIR}/devices/${MCU_VARIANT}
${SDK_DIR}/devices/${MCU_VARIANT}/drivers
)
if (${FAMILY_MCUS} STREQUAL "MCXN9")
target_sources(${BOARD_TARGET} PRIVATE
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
)
target_include_directories(${BOARD_TARGET} PUBLIC
${SDK_DIR}/drivers/lpflexcomm
)
elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
target_sources(${BOARD_TARGET} PRIVATE
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c
)
endif()
update_board(${BOARD_TARGET})

21
hw/bsp/mcx/family.mk
View File

@@ -35,18 +35,19 @@ SRC_C += \
$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
${SDK_DIR}/drivers/gpio/fsl_gpio.c \
${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \
${SDK_DIR}/drivers/common/fsl_common_arm.c\
hw/bsp/mcx/drivers/spc/fsl_spc.c
# fsl_lpflexcomm for MCXN9
ifeq ($(MCU_VARIANT), MCXN947)
SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
endif
# fsl_spc for MCXNA15
ifeq ($(MCU_VARIANT), MCXA153)
SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
endif
INC += \
@@ -54,5 +55,15 @@ INC += \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
$(TOP)/$(SDK_DIR)/drivers/ \
$(TOP)/$(SDK_DIR)/drivers/lpuart \
$(TOP)/$(SDK_DIR)/drivers/lpflexcomm \
$(TOP)/$(SDK_DIR)/drivers/common\
$(TOP)/$(SDK_DIR)/drivers/gpio\
$(TOP)/$(SDK_DIR)/drivers/port\
$(TOP)/hw/bsp/mcx/drivers/spc
SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S