add usbd_spin_lock/unlock for driver usage
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@@ -340,15 +340,16 @@ TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8
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enum { RHPORT_INVALID = 0xFFu };
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tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
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// Event queue
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// usbd_int_set() is used as mutex in OS NONE config
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static OSAL_SPINLOCK_DEF(_usbd_spin, usbd_int_set);
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// Event queue: usbd_int_set() is used as mutex in OS NONE config
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OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
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tu_static osal_queue_t _usbd_q;
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static osal_queue_t _usbd_q;
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// Mutex for claiming endpoint
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#if OSAL_MUTEX_REQUIRED
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tu_static osal_mutex_def_t _ubsd_mutexdef;
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tu_static osal_mutex_t _usbd_mutex;
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static osal_mutex_def_t _ubsd_mutexdef;
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static osal_mutex_t _usbd_mutex;
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#else
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#define _usbd_mutex NULL
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#endif
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@@ -466,7 +467,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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TU_ASSERT(rh_init);
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TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport,
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rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
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rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
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TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
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TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t));
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TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
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@@ -475,6 +476,8 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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tu_varclr(&_usbd_dev);
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_usbd_queued_setup = 0;
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osal_spin_init(&_usbd_spin);
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#if OSAL_MUTEX_REQUIRED
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// Init device mutex
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_usbd_mutex = osal_mutex_create(&_ubsd_mutexdef);
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@@ -1250,6 +1253,13 @@ void usbd_int_set(bool enabled) {
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}
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}
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void usbd_spin_lock(bool in_isr) {
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osal_spin_lock(&_usbd_spin, in_isr);
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}
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void usbd_spin_unlock(bool in_isr) {
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osal_spin_unlock(&_usbd_spin, in_isr);
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}
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// Parse consecutive endpoint descriptors (IN & OUT)
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bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
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{
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@@ -68,6 +68,8 @@ usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR
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typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
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void usbd_int_set(bool enabled);
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void usbd_spin_lock(bool in_isr);
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void usbd_spin_unlock(bool in_isr);
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//--------------------------------------------------------------------+
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// USBD Endpoint API
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@@ -57,8 +57,6 @@ typedef struct {
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static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
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static OSAL_SPINLOCK_DEF(_dcd_spinlock, usbd_int_set);
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typedef struct {
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
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@@ -394,7 +392,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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tu_memclr(&_dcd_data, sizeof(_dcd_data));
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osal_spin_init(&_dcd_spinlock);
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// Core Initialization
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const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
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@@ -539,7 +536,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
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osal_spin_lock(&_dcd_spinlock, false);
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usbd_spin_lock(false);
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_dcd_data.allocated_epin_count = 0;
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@@ -560,7 +557,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dfifo_flush_rx(dwc2);
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dfifo_device_init(rhport); // re-init dfifo
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osal_spin_unlock(&_dcd_spinlock, false);
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usbd_spin_unlock(false);
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}
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bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
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@@ -581,7 +578,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
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bool ret;
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osal_spin_lock(&_dcd_spinlock, false);
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usbd_spin_lock(false);
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if (xfer->max_size == 0) {
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ret = false; // Endpoint is closed
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@@ -600,7 +597,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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ret = true;
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}
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osal_spin_unlock(&_dcd_spinlock, false);
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usbd_spin_unlock(false);
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return ret;
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}
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@@ -618,7 +615,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
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xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
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bool ret;
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osal_spin_lock(&_dcd_spinlock, false);
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usbd_spin_lock(false);
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if (xfer->max_size == 0) {
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ret = false; // Endpoint is closed
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@@ -633,7 +630,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
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ret = true;
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}
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osal_spin_unlock(&_dcd_spinlock, false);
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usbd_spin_unlock(false);
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return ret;
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}
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@@ -1022,9 +1019,9 @@ void dcd_int_handler(uint8_t rhport) {
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// USBRST is start of reset.
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dwc2->gintsts = GINTSTS_USBRST;
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osal_spin_lock(&_dcd_spinlock, true);
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usbd_spin_lock(true);
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handle_bus_reset(rhport);
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osal_spin_unlock(&_dcd_spinlock, true);
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usbd_spin_unlock(true);
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}
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if (gintsts & GINTSTS_ENUMDNE) {
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