add usbd_spin_lock/unlock for driver usage

This commit is contained in:
hathach
2025-05-21 11:41:06 +07:00
parent c1d23a0a92
commit 5551a3e430
3 changed files with 26 additions and 17 deletions

View File

@@ -340,15 +340,16 @@ TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8
enum { RHPORT_INVALID = 0xFFu };
tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
// Event queue
// usbd_int_set() is used as mutex in OS NONE config
static OSAL_SPINLOCK_DEF(_usbd_spin, usbd_int_set);
// Event queue: usbd_int_set() is used as mutex in OS NONE config
OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
tu_static osal_queue_t _usbd_q;
static osal_queue_t _usbd_q;
// Mutex for claiming endpoint
#if OSAL_MUTEX_REQUIRED
tu_static osal_mutex_def_t _ubsd_mutexdef;
tu_static osal_mutex_t _usbd_mutex;
static osal_mutex_def_t _ubsd_mutexdef;
static osal_mutex_t _usbd_mutex;
#else
#define _usbd_mutex NULL
#endif
@@ -466,7 +467,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
TU_ASSERT(rh_init);
TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport,
rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t));
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
@@ -475,6 +476,8 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
tu_varclr(&_usbd_dev);
_usbd_queued_setup = 0;
osal_spin_init(&_usbd_spin);
#if OSAL_MUTEX_REQUIRED
// Init device mutex
_usbd_mutex = osal_mutex_create(&_ubsd_mutexdef);
@@ -1250,6 +1253,13 @@ void usbd_int_set(bool enabled) {
}
}
void usbd_spin_lock(bool in_isr) {
osal_spin_lock(&_usbd_spin, in_isr);
}
void usbd_spin_unlock(bool in_isr) {
osal_spin_unlock(&_usbd_spin, in_isr);
}
// Parse consecutive endpoint descriptors (IN & OUT)
bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
{

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@@ -68,6 +68,8 @@ usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR
typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
void usbd_int_set(bool enabled);
void usbd_spin_lock(bool in_isr);
void usbd_spin_unlock(bool in_isr);
//--------------------------------------------------------------------+
// USBD Endpoint API

View File

@@ -57,8 +57,6 @@ typedef struct {
static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
static OSAL_SPINLOCK_DEF(_dcd_spinlock, usbd_int_set);
typedef struct {
// EP0 transfers are limited to 1 packet - larger sizes has to be split
uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
@@ -394,7 +392,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
tu_memclr(&_dcd_data, sizeof(_dcd_data));
osal_spin_init(&_dcd_spinlock);
// Core Initialization
const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
@@ -539,7 +536,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
osal_spin_lock(&_dcd_spinlock, false);
usbd_spin_lock(false);
_dcd_data.allocated_epin_count = 0;
@@ -560,7 +557,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
dfifo_flush_rx(dwc2);
dfifo_device_init(rhport); // re-init dfifo
osal_spin_unlock(&_dcd_spinlock, false);
usbd_spin_unlock(false);
}
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
@@ -581,7 +578,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
bool ret;
osal_spin_lock(&_dcd_spinlock, false);
usbd_spin_lock(false);
if (xfer->max_size == 0) {
ret = false; // Endpoint is closed
@@ -600,7 +597,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
ret = true;
}
osal_spin_unlock(&_dcd_spinlock, false);
usbd_spin_unlock(false);
return ret;
}
@@ -618,7 +615,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
bool ret;
osal_spin_lock(&_dcd_spinlock, false);
usbd_spin_lock(false);
if (xfer->max_size == 0) {
ret = false; // Endpoint is closed
@@ -633,7 +630,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
ret = true;
}
osal_spin_unlock(&_dcd_spinlock, false);
usbd_spin_unlock(false);
return ret;
}
@@ -1022,9 +1019,9 @@ void dcd_int_handler(uint8_t rhport) {
// USBRST is start of reset.
dwc2->gintsts = GINTSTS_USBRST;
osal_spin_lock(&_dcd_spinlock, true);
usbd_spin_lock(true);
handle_bus_reset(rhport);
osal_spin_unlock(&_dcd_spinlock, true);
usbd_spin_unlock(true);
}
if (gintsts & GINTSTS_ENUMDNE) {