Replace cache clean/invalidate by MPU config.
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@@ -33,19 +33,6 @@
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
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#include "ci_hs_imxrt.h"
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void dcd_dcache_clean(void const* addr, uint32_t data_size) {
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imxrt_dcache_clean(addr, data_size);
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}
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void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
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imxrt_dcache_invalidate(addr, data_size);
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}
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void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
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imxrt_dcache_clean_invalidate(addr, data_size);
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}
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#else
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#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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@@ -57,18 +44,6 @@
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#else
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#error "Unsupported MCUs"
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#endif
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TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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}
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TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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}
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TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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}
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#endif
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//--------------------------------------------------------------------+
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@@ -230,8 +205,6 @@ static void bus_reset(uint8_t rhport)
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_dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
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_dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
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dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
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}
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bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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@@ -257,8 +230,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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#endif
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dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
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@@ -325,10 +296,6 @@ void dcd_sof_enable(uint8_t rhport, bool en)
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static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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{
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// Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
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// address to 32-byte boundaries. Buffer must be word aligned
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dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
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tu_memclr(p_qtd, sizeof(dcd_qtd_t));
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p_qtd->next = QTD_NEXT_INVALID;
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@@ -402,8 +369,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
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// Enable EP Control
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uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
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@@ -461,9 +426,6 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
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p_qhd->qtd_overlay.halted = false; // clear any previous error
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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// flush cache
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dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
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if ( epnum == 0 )
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{
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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@@ -539,8 +501,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
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page++;
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}
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}
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dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
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}
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else
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{
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@@ -652,9 +612,6 @@ void dcd_int_handler(uint8_t rhport)
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if (int_status & INTR_USB)
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{
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// Make sure we read the latest version of _dcd_data.
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dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
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uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
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dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
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