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ehci clean up

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This commit is contained in:
hathach
2018-12-10 20:16:26 +07:00
parent 4e7596ca9c
commit 5886ccdb03
4 changed files with 18 additions and 38 deletions
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38
src/host/ehci/ehci.c
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@@ -80,7 +80,6 @@ static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLI
static inline ehci_qhd_t* qhd_find_free (uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
static inline tusb_xfer_type_t qhd_get_xfer_type(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
static inline ehci_qhd_t* qhd_get_from_pipe_handle(uint8_t dev_addr, pipe_handle_t pipe_hdl);
static inline pipe_handle_t qhd_create_pipe_handle(ehci_qhd_t const * p_qhd);
// determine if a queue head has bus-related error
static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd)
@@ -91,7 +90,6 @@ static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd)
static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd ) ATTR_PURE ATTR_ALWAYS_INLINE;
static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) ATTR_ALWAYS_INLINE;
@@ -557,30 +555,30 @@ static void async_advance_isr(ehci_qhd_t * const async_head)
_usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
}
for(uint8_t relative_dev_addr=0; relative_dev_addr < CFG_TUSB_HOST_DEVICE_MAX; relative_dev_addr++)
for(uint8_t dev_addr=1; dev_addr < CFG_TUSB_HOST_DEVICE_MAX; dev_addr++)
{
// check if control endpoint is removing
ehci_qhd_t *p_control_qhd = &ehci_data.device[relative_dev_addr].control.qhd;
ehci_qhd_t *p_control_qhd = get_control_qhd(dev_addr);
if ( p_control_qhd->is_removing )
{
p_control_qhd->is_removing = 0;
p_control_qhd->used = 0;
// Host Controller has cleaned up its cached data for this device, set state to unplug
_usbh_devices[relative_dev_addr+1].state = TUSB_DEVICE_STATE_UNPLUG;
_usbh_devices[dev_addr+1].state = TUSB_DEVICE_STATE_UNPLUG;
for (uint8_t i=0; i<HCD_MAX_ENDPOINT; i++) // free all qhd
{
ehci_data.device[relative_dev_addr].qhd[i].used = 0;
ehci_data.device[relative_dev_addr].qhd[i].is_removing = 0;
ehci_data.device[dev_addr].qhd[i].used = 0;
ehci_data.device[dev_addr].qhd[i].is_removing = 0;
}
for (uint8_t i=0; i<HCD_MAX_XFER; i++) // free all qtd
{
ehci_data.device[relative_dev_addr].qtd[i].used = 0;
ehci_data.device[dev_addr].qtd[i].used = 0;
}
// TODO free all itd & sitd
}
} // end for device[] loop
}
}
static void port_connect_status_change_isr(uint8_t hostid)
@@ -827,7 +825,7 @@ static inline ehci_registers_t* get_operational_register(uint8_t hostid)
//------------- queue head helper -------------//
static inline ehci_qhd_t* get_async_head(uint8_t hostid)
{
return &ehci_data.dev0.qhd;
return get_control_qhd(0);
}
#if EHCI_PERIODIC_LIST // TODO refractor/group this together
@@ -839,13 +837,11 @@ static inline ehci_link_t* get_period_head(uint8_t hostid, uint8_t interval_ms)
static inline ehci_qhd_t* get_control_qhd(uint8_t dev_addr)
{
return (dev_addr == 0) ?
get_async_head( _usbh_devices[dev_addr].rhport ) :
&ehci_data.device[dev_addr-1].control.qhd;
return &ehci_data.control[dev_addr].qhd;
}
static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr)
{
return (dev_addr == 0) ? &ehci_data.dev0.qtd : &ehci_data.device[ dev_addr-1 ].control.qtd;
return &ehci_data.control[dev_addr].qtd;
}
static inline ehci_qhd_t* qhd_find_free (uint8_t dev_addr)
@@ -880,20 +876,6 @@ static inline ehci_qhd_t* qhd_get_from_pipe_handle(uint8_t dev_addr, pipe_handle
return &ehci_data.device[dev_addr-1].qhd[pipe_hdl.index];
}
static inline pipe_handle_t qhd_create_pipe_handle(ehci_qhd_t const * p_qhd)
{
pipe_handle_t pipe_hdl = { };
// TODO Isochronous transfer support
if (TUSB_XFER_CONTROL != p_qhd->xfer_type) // qhd index for control is meaningless
{
pipe_hdl.index = qhd_get_index(p_qhd);
pipe_hdl.ep_addr = edpt_addr(p_qhd->endpoint_number, p_qhd->pid_non_control == EHCI_PID_IN ? 1 : 0);
}
return pipe_hdl;
}
//------------- TD helper -------------//
static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr)
{

10
src/host/ehci/ehci.h
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@@ -456,17 +456,13 @@ typedef struct
// [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
ehci_qhd_t period_head_arr[4];
// Note control qhd of dev0 is used as head of async list, always exists
struct {
ehci_qhd_t qhd; // also used as head of async list (each for 1 controller), always exists
ehci_qtd_t qtd;
}dev0;
struct {
struct {
ehci_qhd_t qhd;
ehci_qtd_t qtd;
}control;
}control[CFG_TUSB_HOST_DEVICE_MAX+1];
struct {
ehci_qhd_t qhd[HCD_MAX_ENDPOINT] ; ///< Queue Head Pool
ehci_qtd_t qtd[HCD_MAX_XFER] ATTR_ALIGNED(32) ; ///< Queue Element Transfer Pool
// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool

6
src/host/hcd.h
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@@ -87,15 +87,17 @@ enum {
HCD_MAX_XFER = HCD_MAX_ENDPOINT*2,
};
//#define HCD_MAX_ENDPOINT 16
//#define HCD_MAX_XFER 16
#endif
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
typedef struct {
uint8_t ep_addr;
uint8_t index;
uint8_t reserved[2];
uint8_t reserved[3];
} pipe_handle_t;
static inline bool pipehandle_is_valid(pipe_handle_t pipe_hdl)

2
src/host/usbh.c
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@@ -273,7 +273,7 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t ev
}
else
{
TU_ASSERT(false, ); // something wrong, no one claims the isr's source
TU_BREAKPOINT(); // something wrong, no one claims the isr's source
}
}
}