pi cm4 enumerated as full speed device
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@@ -60,12 +60,23 @@ typedef struct
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__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */
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uint32_t Reserved30[2]; /*!< Reserved 030h*/
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__IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */
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__IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */
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uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */
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__IO uint32_t CID; /*!< User ID Register 03Ch */
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__IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
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__IO uint32_t GHWCFG1; /* User HW config1 044h*/
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__IO uint32_t GHWCFG2; /* User HW config2 048h*/
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__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
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uint32_t Reserved6; /*!< Reserved 050h */
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__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
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__IO uint32_t GPWRDN; /*!< Power Down Register 058h */
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__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
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__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
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uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
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__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */
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__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */
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} USB_OTG_GlobalTypeDef;
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/**
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* @brief __device_Registers
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*/
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