From 5f473d51cf04a7bfeca71bce09a9b3a4c2b2a7d1 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 18 Apr 2024 20:00:45 +0200 Subject: [PATCH] Fix IAR breakpoint test. --- src/common/tusb_verify.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 8aa66b4df..71406dacf 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -76,7 +76,8 @@ #endif // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \ + defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define TU_BREAKPOINT() do \ { \ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \