Fix IAR breakpoint test.
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		| @@ -76,7 +76,8 @@ | ||||
| #endif | ||||
|  | ||||
| // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55 | ||||
| #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) | ||||
| #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \ | ||||
|     defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) | ||||
|   #define TU_BREAKPOINT() do                                                                                \ | ||||
|   {                                                                                                         \ | ||||
|     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ | ||||
|   | ||||
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